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參數資料
| 型號： | EVAL-AD5663REBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 14/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5663 |
| 產品培訓模塊： | DAC Architectures |
| 標準包裝： | 1 |
| 系列： | nanoDAC™ |
| DAC 的數量： | 2 |
| 位數： | 16 |
| 采樣率（每秒）： | 220k |
| 數據接口： | 串行 |
| 設置時間： | 4µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 105°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD5663 |
| 相關產品： | AD5663RBCPZ-3R2TR-ND - IC DAC NANO 16BIT DUAL 10-LFCSP AD5663BCPZ-R2TR-ND - IC DAC NANO 16BIT DUAL 10-LFCSP AD5663RBCPZ-3REEL7DKR-ND - IC DAC NANO 16BIT 1.25V 10-LFCSP AD5663BCPZ-REEL7DKR-ND - IC DAC NANO 16BIT DUAL 10-LFCSP AD5663RBCPZ-3REEL7CT-ND - IC DAC NANO 16BIT 1.25V 10-LFCSP AD5663BCPZ-REEL7CT-ND - IC DAC NANO 16BIT DUAL 10-LFCSP AD5663RBRMZ-5-ND - IC DAC NANO 16BIT 2.5V 10-MSOP AD5663RBRMZ-3-ND - IC DAC NANO 16BIT 1.25V 10-MSOP AD5663BRMZ-1-ND - IC DAC NANO 16BIT DUAL 10-MSOP AD5663BRMZ-ND - IC DAC NANO 16BIT DUAL 10-MSOP 更多... |
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Data Sheet
AD5623R/AD5643R/AD5663R
Rev. E | Page 21 of 32
At this stage, the SYNC line can be kept low or be brought high.
In either case, it must be brought high for a minimum of 15 ns
before the next write sequence, so that a falling edge of SYNC
can initiate the next write sequence.
Because the SYNC buffer draws more current when VIN = 2 V
than it does when VIN = 0.8 V, SYNC should be idled low between
write sequences for even lower power operation. As mentioned
previously, it must, however, be brought high again just before
the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide (see Figure 52). The first
two bits are don’t cares. The next three are Command Bit C2 to
Command Bit C0 (see Table 8), followed by the 3-bit DAC
Address A2 to DAC Address A0 (see Table 9), and, finally, the
16-, 14-, and 12-bit data-word.
The data-word comprises the 16-, 14-, and 12-bit input codes,
followed by zero, two, or four don’t care bits, for the AD5663R,
AD5643R, and AD5623R, respectively (see Figure 51, Figure 52,
and Figure 53). The data bits are transferred to the DAC register
on the 24th falling edge of SCLK.
Table 8. Command Definition
C2
C1
C0
Command
0
Write to Input Register n
0
1
Update DAC Register n
0
1
0
Write to Input Register n, update all
(software LDAC)
0
1
Write to and update DAC Channel n
1
0
Power down DAC (power up)
1
0
1
Reset
1
0
LDAC register setup
1
Internal reference setup (on/off)
Table 9. Address Command
A2
A1
A0
ADDRESS (n)
0
DAC A
0
1
DAC B
0
1
0
Reserved
0
1
Reserved
1
All DACs
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 24 falling edges of SCLK, and the DAC is updated on the
24th falling edge. However, if SYNC is brought high before the
24th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 54).
X
C2
C1
C0
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DB23 (MSB)
DB0 (LSB)
COMMAND BITS
ADDRESS BITS
DATA BITS
05858-
034
Figure 51. AD5663R Input Shift Register Contents
X
C2
C1
C0
A2
A1
A0
X
D11
D10
D13
D12
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DB23 (MSB)
DB0 (LSB)
COMMAND BITS
ADDRESS BITS
DATA BITS
05858-
071
Figure 52. AD5643R Input Shift Register Contents
X
C2
C1
C0
A2
A1
A0
X
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DB23 (MSB)
DB0 (LSB)
COMMAND BITS
ADDRESS BITS
DATA BITS
05858-
072
Figure 53. AD5623R Input Shift Register Contents
DIN
DB23
DB0
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 24TH FALLING EDGE
SYNC
SCLK
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 24TH FALLING EDGE
05858-
035
Figure 54. SYNC Interrupt Facility
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| EVAL-AD5664REB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/C On-Chip Reference |
| EVAL-AD5664REBZ | 功能描述:BOARD EVALUATION FOR AD5664R RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數模轉換器 (DAC) 系列:nanoDAC™ 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數量:4 位數:12 采樣率（每秒）:- 數據接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-AD5665REBZ1 | 功能描述:BOARD EVAL FOR AD5665 TSSOP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數模轉換器 (DAC) 系列:* 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數量:4 位數:12 采樣率（每秒）:- 數據接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-AD5665REBZ2 | 功能描述:BOARD EVAL FOR AD5665 LFCSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數模轉換器 (DAC) 系列:* 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數量:4 位數:12 采樣率（每秒）:- 數據接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-AD5666EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad, 16-Bit DAC with 5 ppm/C On-Chip Reference in 14-Lead TSSOP |
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