10. Calculate FZ, the ESR zero frequency, usin" />
參數(shù)資料
型號： EVAL-AD5560EBUZ
廠商： Analog Devices Inc
文件頁數(shù)： 33/68頁
文件大小： 0K
描述： BOARD EVALUATION FOR AD5560
標(biāo)準包裝： 1
主要目的： 電源管理，電源監(jiān)控器/跟蹤器/序列發(fā)生器
已用 IC / 零件： AD5560
次要屬性： 串行接口
已供物品： 板
Data Sheet
AD5560
Rev. D | Page 39 of 68
10. Calculate FZ, the ESR zero frequency, using FZ =
1/(2πRcCr).
11. If FP > Fug, the load pole is above the bandwidth of the
AD5560. Ignore it with RZ[2:0] = 0, RP[2:0] = 0. This ends the
algorithm
12. If RC < (R0/25), then the ESR is negligible. Attempt to
cancel the load pole with RZ zero. Choose an ideal zero
frequency of 2 × FP for some safety margin and then
choose the RZ[2:0] value that gives the closest frequency on a
logarithmic scale. This ends the algorithm
13. Otherwise, this is a troublesome window in which a load
pole and a load zero can’t be ignored. Use the following
steps:
To cancel the load pole at FP, choose an ideal zero
frequency of 6 × FP (this is more conservative than the
2 × FP suggested earlier, but there is more that can go
wrong with miscalculation). Then choose the RZ[2:0]
value that gives the closest zero to this ideal frequency
of 6 × FP on a logarithmic scale.
To cancel the ESR zero at FZ, choose an ideal pole
frequency of 2 × FZ.
Then choose the RP[2:0] value that gives the closest pole
to this ideal frequency of 2 × FZon a logarithmic scale.
This ends the algorithm
ADJUSTING THE AUTOCOMPENSATION MODE
The autocompensation algorithm assumes that there is 1 Ω of
resistance (RC) from the AD5560 to the DUT. If a particular
application has resistance that differs greatly from this, then
it is likely that the autocompensation algorithm is nonoptimal.
If using the autocompensation algorithm as a starting point,
consider that overstating the CR capacitance and understating
the ESR RC is likely to give a faster response but could cause
oscillations. Understating CR and overstating RC is more likely
to slow things down and reduce phase margin but not create
an oscillator.
It is often advisable to err on the side of simplicity. Rather than
insert a pole and zero at similar frequencies, it may be better to
add none at all. Set RP[2:0] = RZ[2:0] = 0 to push them beyond the
AD5560 bandwidth.
DEALING WITH PARALLEL LOAD CAPACITORS
In the event that the load capacitance consists of two parallel
capacitors with different ESRs, it is highly likely that the overall
complex impedance at the unity gain bandwidth is dominated
by the larger capacitor and its ESR. Assuming that the smaller
capacitor does not exist normally is a safer simplifying assump-
tion.
A more complex alternative is to calculate the overall impedance
at the expected unity gain bandwidth and use this to calculate
an equivalent series CR and RC that have the same complex
impedance at that particular frequency.
DAC LEVELS
This device contains all the dedicated DAC levels necessary
for operation: a 16-bit DAC for the force amplifier, two 16-bit
DACs for the clamp high and low levels, two 16-bit DACs for
the comparator high and low levels, a 16-bit DAC to set a
programmable open sense voltage, and a 16-bit offset DAC
to bias or offset a number of DACs on chip (FORCE, CLL,
CLH, CPL, CPH).
FORCE AND COMPARATOR DACS
The architecture of the main force amplifier DAC consists of
a 16-bit R-2R DAC, whereas the comparator DACs are resistor-
string DACs followed by an output buffer amplifier. This
resistor-string architecture guarantees DAC monotonicity.
The 16-bit binary digital code loaded to the DAC register
determines at what node on the string the voltage is tapped
off before being fed to the output amplifier.
The comparator DAC is similarly arranged. The force and
comparator DACs have a 25.62 V span, including overrange
to enable offset and gain errors to be calibrated out.
The transfer function for these 16-bit DACs is
DUTGND
CODE
DAC
OFFSET
VREF
CODE
DAC
VREF
V
OUT
+
×
×
=
16
2
_
125
.
5
2
125
.
5
where DAC CODE is X2 (see the Offset and Gain Registers
section).
CLAMP DACS
The architecture of the clamp DAC consists of a 16-bit resistor-
string DAC followed by an output buffer amplifier. This resistor-
string architecture guarantees DAC monotonicity. The 16-bit
binary digital code loaded to the DAC register determines at
what node on the string the voltage is tapped off before being
fed to the output amplifier.
The clamp DACs have a 25.62 V span, including overrange, to
enable offset and gain errors to be calibrated out.
相關(guān)PDF資料
PDF描述
EVAL-AD5522EBDZ BOARD EVAL FOR 14X14MM AD5522
EVAL-AD5520EBZ BOARD EVAL FOR AD5520
MAX6198AESA+T IC VREF SERIES PREC 4.096V 8SOIC
QPI-5-EVAL1 EVALUATION BOARD FOR QPI-5
H6MMH-4006M DIP CABLE - HDM40H/AE40M/HDM40H
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-AD5570EB 制造商:Analog Devices 功能描述:DEV TOOLS, TRUE ACCURACY, 16BIT 12V/ 15V, SERL INPUT VOLT O - Bulk
EVAL-AD5570EBZ 功能描述:BOARD EVALUATION FOR AD5570 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5570SDZ 功能描述:BOARD EVAL FOR AD5570 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5590EBZ 功能描述:BOARD EVAL FOR AD5590 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
EVAL-AD5620EB 制造商:AD 制造商全稱:Analog Devices 功能描述:Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*