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參數(shù)資料
| 型號： | EVAL-AD5520EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5520 |
| 標準包裝： | 1 |
| 主要目的： | 測試與測量，每引腳參數(shù)測量單元（PPMU） |
| 已用 IC / 零件： | AD5520 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD5520JSTZ-ND - IC PPMU SNGL-CH 64-LQFP |
AD5520
Rev. B | Page 22 of 24
EVALUATION BOARD FOR THE AD5520
A full-featured evaluation kit is available for the AD5520. It
includes an evaluation board with direct hookup via a 36-way
Centronics connector to a PC. PC-based software to control the
AD5520 is also part of the evaluation kit. The evaluation board
schematic is shown in Figure 28.
Note that VDD and VSS must provide sufficient headroom for the
force and measure voltage range. In addition to the supply
voltages for the evaluation board, it is necessary to provide the
voltage levels for the clamp, comparator, and the force input
pins (CLL, CLH, CPL, CPH, and FIN). SMB connections are
provided for these voltage inputs. To use the evaluation board, it
is also necessary to provide a DUT connected via the gold pins.
Both AGND and DGND inputs are provided on the board. The
AGND and DGND planes are connected at one location close
to the AD5520. It is recommended not to connect AGND and
DGND elsewhere in the system to avoid ground loop problems.
REFGND is routed back to AGND at the power block to
maintain a clean ground reference for accurate measurements.
Each supply is decoupled to the relevant ground plane with
10 μF and 0.1 μF capacitors. The device supply pin is again
decoupled with a 10 μF and 0.1 μF capacitor pair to the relevant
ground plane.
Care should be taken when replacing devices to ensure that the
pins line up correctly with the PCB pads.
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