參數(shù)資料
型號： EVAL-AD1940MINIBZ
廠商： Analog Devices Inc
文件頁數(shù)： 36/36頁
文件大?。?/td> 0K
描述： BOARD EVAL AD1940 MINI SIGMADSP
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
主要目的： 音頻，音頻處理
嵌入式： 是，DSP
已用 IC / 零件： AD1940
主要屬性： 單芯片多通道 28/56 位音頻 DSP
次要屬性： 均衡，交叉，低音增強，多頻帶動態(tài)處理，延遲等
已供物品： 板，線纜，CD，電源，USB 適配器
產(chǎn)品目錄頁面： 775 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD1940YSTZ-ND - IC DSP AUDIO 16CH/28BIT 48-LQFP
AD1940YSTZRL-ND - IC DSP AUDIO 16CH/28BIT 48-LQFP
AD1940/AD1941
Rev. B | Page 9 of
36
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
GND
BCLK_OUT1
LRCLK_OUT1
ODVDD
SDATA_OUT3
SDATA_OUT2
SDATA_OUT1
VDD
MCLK
RESERVED
PLL_VDD
NC
SDATA_OUT0
ODVDD
BCLK_OUT0
LRCLK_OUT0
GND
VDD
PIN 1
INDICATOR
PLL_CTRL0
PLL_CTRL1
PLL_CTRL2
PLL_GND
AD1940
TOP VIEW
(Not to Scale)
V
D
S
D
A
T
A
_
IN
1
S
D
A
T
A
_
IN
2
S
D
A
T
A
_
IN
3
C
O
U
T
C
L
K
C
L
A
T
C
H
C
D
A
T
A
R
E
S
E
T
B
G
N
D
S
DATA_
IN0
ADR_
S
E
L
GN
D
VRE
F
VDR
IV
E
V
SEN
S
E
VS
UP
PLY
IN
V
D
SDA
T
A_
OUT7
SDA
T
A_O
U
T6
O
DV
DD
SDA
T
A_O
U
T5
SD
AT
A
_
O
U
T
4
VDD
04607-0-002
LRCLK_IN
BCLK_IN
NC = NO CONNECT
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
GND
BCLK_OUT1
LRCLK_OUT1
ODVDD
SDATA_OUT3
SDATA_OUT2
SDATA_OUT1
VDD
MCLK
RESERVED
PLL_VDD
I2C_FILT_EN
SDATA_OUT0
ODVDD
BCLK_OUT0
LRCLK_OUT0
GND
VDD
PIN 1
INDICATOR
PLL_CTRL0
PLL_CTRL1
PLL_CTRL2
PLL_GND
AD1941
TOP VIEW
(Not to Scale)
VD
D
S
DATA
_I
N1
S
DATA
_
IN2
S
DATA
_
IN3
SD
A
SC
L
NC
RE
SETB
GN
D
S
DATA_
IN0
ADR_
S
E
L
GN
D
VRE
F
VDR
IV
E
V
SEN
S
E
VS
UP
PLY
IN
V
D
SDA
T
A_
OUT7
SDA
T
A_O
U
T6
O
DV
DD
SDA
T
A_O
U
T5
SD
AT
A
_
O
U
T
4
VDD
04607-0-011
LRCLK_IN
BCLK_IN
NC = NO CONNECT
Figure 7. 48-Lead LQFP Pin Configuration, AD1940
Figure 8. 48-Lead LQFP Pin Configuration, AD1941
Table 10. Pin Function Descriptions
Pin No.
AD1940
AD1941
I/O
Mnemonic
Description
1, 25, 37
VDD
Core Power.
2
IN
MCLK
Master Clock Input.
3
RESERVED
This pin should be connected to ground.
4
IN
PLL_CTRL0
PLL Control 0.
5
IN
PLL_CTRL1
PLL Control 1.
6
IN
PLL_CTRL2
PLL Control 2.
7
PLL_GND
PLL Ground.
8
PLL_VDD
PLL Power.
9
21, 22
NC
No Connect.
9
IN
I2C_FILT_ENB
I2C Filter Enable, Active Low.
10
IN
LRCLK_IN
Left/Right Clock for Serial or TDM Data Inputs.
11
IN
BCLK_IN
Bit Clock for Serial or TDM Data Inputs.
12, 24, 36,
48
12, 24, 36,
48
GND
Digital Ground.
13
VDD
Core Power.
14
IN
SDATA_IN0
Serial Data Input 0.
15
12
IN
SDATA_IN1
Serial Data Input 1.
16
IN
SDATA_IN2/TDM_IN1
Serial Data Input 2/TDM Input 1.
17
IN
SDATA_IN3/TDM_IN0
Serial Data Input 3/TDM Input 0.
18
IN
ADR_SEL
Control Port Address Select.
19
OUT
COUT
SPI Data Output.
20
IN
CCLK
Clock for SPI.
21
IN
CLATCH
SPI Data Latch.
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