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參數(shù)資料
| 型號(hào)： | EV-ADF4360-3EB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 9/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADF4360-3 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4360-3 |
| 主要屬性： | 帶 VCO 的單路整數(shù)-N PLL |
| 次要屬性： | 1.8GHz，200kHz PFD |
| 已供物品： | 板，纜線(xiàn)，CD |
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Data Sheet
ADF4360-3
Rev. D | Page 17 of 24
Hardware Power-Up/Power-Down
If the part is powered down via the hardware (using the CE pin)
and powered up again without any change to the N counter
register during power-down, the part locks at the correct fre-
quency because the part is already in the correct frequency
band. The lock time depends on the value of capacitance on the
CN pin, which is <5 ms for 10 F capacitance. The smaller ca-
pacitance of 440 nF on this pin enables lock times of <600 s.
The N counter value cannot be changed while the part is in
power-down, since the part may not lock to the correct fre-
quency on power-up. If it is updated, the correct programming
sequence for the part after power-up is to the R counter latch,
followed by the control latch, and finally the N counter latch,
with the required interval between the control latch and N
counter latch, as described in the Initial Power-Up section.
Software Power-Up/Power-Down
If the part is powered down via the software (using the control
latch) and powered up again without any change to the N coun-
ter latch during power-down, the part locks at the correct fre-
quency because the part is already in the correct frequency
band. The lock time depends on the value of capacitance on the
CN pin, which is <5 ms for 10 F capacitance. The smaller ca-
pacitance of 440 nF on this pin enables lock times of <600 s.
The N counter value cannot be changed while the part is in
power-down because the part may not lock to the correct fre-
quency on power-up. If it is updated, the correct programming
sequence for the parts after power-up is to the R counter latch,
followed by the control latch, and finally the N counter latch,
with the required interval between the control latch and N
counter latch, as described in the Initial Power-Up section.
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