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參數(shù)資料
| 型號(hào)： | EV-ADF4360-3EB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADF4360-3 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4360-3 |
| 主要屬性： | 帶 VCO 的單路整數(shù)-N PLL |
| 次要屬性： | 1.8GHz，200kHz PFD |
| 已供物品： | 板，纜線，CD |
ADF4360-3
Data Sheet
Rev. D | Page 16 of 24
POWER-UP
Power-Up Sequence
The correct programming sequence for the ADF4360-3 after
power-up is:
1. R counter latch
2. Control latch
3. N counter latch
Initial Power-Up
Initial power-up refers to programming the part after the
application of voltage to the AVDD, DVDD, VVCO, and CE pins. On
initial power-up, an interval is required between programming
the control latch and programming the N counter latch.
This interval is necessary to allow the transient behavior of the
ADF4360-3 during initial power-up to have settled. During
initial power-up, a write to the control latch powers up the part,
and the bias currents of the VCO begins to settle. If these cur-
rents have not settled to within 10% of their steady-state value,
and if the N counter latch is then programmed, the VCO may
not be able to oscillate at the desired frequency, which does not
allow the band select logic to choose the correct frequency
band, and the ADF4360-3 may not achieve lock. If the recom-
mended interval is inserted, and the N counter latch is pro-
grammed, the band select logic can choose the correct frequen-
cy band, and the part locks to the correct frequency.
The duration of this interval is affected by the value of the ca-
pacitor on the CN pin (Pin 14). This capacitor is used to reduce
the close-in noise of the ADF4360-3 VCO. The recommended
value of this capacitor is 10 F. Using this value requires an in-
terval of ≥ 5 ms between the latching in of the control latch bits
and latching in of the N counter latch bits. If a shorter delay is
required, this capacitor can be reduced. A slight phase noise
penalty is incurred by this change, which is explained further
Table 10. CN Capacitance vs. Interval and Phase Noise
CN Value
Recommended Interval between Control Latch and N Counter latch
Open-Loop Phase Noise @ 10 kHz Offset
10 F
≥5 ms
87 dBc
440 nF
≥600 s
86 dBc
CLOCK
POWER-UP
DATA
LE
R COUNTER
LATCH DATA
CONTROL
LATCH DATA
N COUNTER
LATCH DATA
REQUIRED INTERVAL
CONTROL LATCH WRITE TO
N COUNTER LATCH WRITE
04437-020
Figure 16. ADF4360-3 Power-Up Timing
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