參數(shù)資料
型號(hào)： EV-ADF4157SD1Z
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 12/24頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR ADF4157
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，頻率合成器
嵌入式： 否
已用 IC / 零件： ADF4157
主要屬性： 單路分?jǐn)?shù)-N PLL
次要屬性： 6GHz
已供物品： 板
ADF4157
Data Sheet
Rev. D | Page 2 of 24
TABLE OF CONTENTS
REVISION HISTORY
8/12—Rev. C to Rev. D
Changes to Figure 4 and Table 5......................................................6
Updated Outline Dimensions (Changed CP-20-1 to CP-20-6) .....22
Changes to Ordering Guide ...........................................................21
Criticizing
3/12—Rev. B to Rev. C
Changes to Table 1............................................................................ 3
Changes to Ordering Guide .......................................................... 21
9/11—Rev. A to Rev. B
Changes to Noise Characteristics Parameter ................................ 3
Changes to EPAD Note.................................................................... 6
1/09—Rev. 0 to Rev. A
Changes to Figure 1.......................................................................... 1
Changes to Reference Characteristics Parameter, Table 1 .......... 3
Changes to Table 3............................................................................ 5
Changes to Figure 4 and Table 5......................................................6
Changes to Figure 15...................................................................... 10
Changes to Figure 16...................................................................... 11
Changes to Figure 17...................................................................... 12
Changes to Figure 19...................................................................... 15
Added Negative Bleed Current Section, CLK Divider Mode
Section, and 12-Bit Clock Divider Value Section....................... 17
Changes to Reserved Bits Section and Figure 21 ....................... 17
Deleted Interfacing Section........................................................... 18
Added Fastlock Timer and Register Sequences Section,
Fastlock: An Example Section, and Fastlock: Loop Filter
Topology Section ............................................................................ 19
Added Figure 22 and Figure 23; Renumbered Sequentially ..... 19
Added Operating with Wide Loop Filter Bandwidths
Section.............................................................................................. 20
Updated Outline Dimensions....................................................... 21
7/07—Revision 0: Initial Version
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