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參數(shù)資料
| 型號(hào)： | ES4428 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Web/DVD Set-Top Box Solution |
| 中文描述： | 網(wǎng)絡(luò)/影碟機(jī)頂盒解決方案 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大?。?/td> | 119K |
| 代理商： | ES4428 |
6
SAM0358-052201
ESS Technology, Inc.
ES4428/ES4427 PRODUCT BRIEF
Name
AUX8
TWS
SPLL_OUT
AUX9
TSD
TBCK
RWS
Number
18
19
I/O
I/O
I
O
I/O
I
I
O
I
Definition
General purpose I/O.
Transmit audio frame sync.
SPLL_OUT is the select PLL output.
General purpose I/O.
Transmit audio data input.
Transmit audio bit clock.
Receive audio frame sync.
System and DSCK output clock frequency selection at reset time. The matrix
below lists the available clock frequencies and their respective PLL bit settings..
20
21
22
23
SEL_PLL1
RSTOUT#
RSD
SEL_PLL0
AUX10
AUX11
AUX12
RBCK
24
O
O
I
I/O
I/O
I/O
O
I
Reset output.
Receive audio data input.
Refer to the description and matrix for SEL_PLL1 pin 23.
General purpose I/O.
Interrupt output to ES4428.
CD loader C2PO.
Receive audio bit output clock.
SER_IN is the serial input DSC mode. 1 = Serial DSC mode. 0 = Parallel DSC
mode.
General purpose I/O.
Interrupt input from Modem DSP.
IR interrupt Input.
Audio analog ground.
ADC Common Mode Reference (CMR) buffer output. CMR is approximately 2.25
V. Bypass to analog ground with 47
μ
F electrolytic in parallel with 0.1
μ
F.
DAC and ADC maximum reference. Bypass to VCMR with 10
μ
F in parallel with 0.1
μ
F.
5.0V analog audio power supply.
33
34
35
36
37
SER_IN
AUX13
AUX14
AUX15
VSSAA
38
39
40
I/O
I/O
I/O
I
I
41,51
VCM
42
VREFP
43
I
VCCAA
AOR+,
AOR-
AOL-, AOL+
MIC2
MIC1
44
I
45, 46
O
Right channel output.
47, 48
49
50
O
I
I
I
Left channel output.
Microphone input 2.
Microphone input 1.
Internal resistor divider generates Common Mode Reference (CMR) voltage.
Bypass to analog ground with 0.1
μ
F.
DAC and ADC minimum reference. Bypass to VCMR with 10
μ
F in parallel
with 0.1
μ
F.
Full scale DAC current adjustment.
Compensation pin.
Video analog ground
Modulated chrominance output.
Video VCC, 5 V
VREF
52
VREFM
53
I
RSET
COMP
VSSAV
CDAC
VCCAV
54
55
I
I
I
56:57, 62:63
58
59, 60
O
I
Table 2 ES4427 Pin Descriptions (Continued)
SEL_PLL1
0
0
1
1
SEL_PLL0
0
1
0
1
DCLK
Bypass PLL (input mode)
27 MHz (output mode) Default
32.4 MHz (output mode)
40.5 MHz (output mode)
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