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參數(shù)資料
| 型號： | ES4428 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Web/DVD Set-Top Box Solution |
| 中文描述： | 網(wǎng)絡(luò)/影碟機頂盒解決方案 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大小： | 119K |
| 代理商： | ES4428 |
3
SAM0358-052201
ESS Technology, Inc.
ES4428/ES4427 PRODUCT BRIEF
ES4428 PIN DESCRIPTION
Table 1 lists the pin descriptions for the ES4428.
Table 1 ES4428 Pin Descriptions
Name
1, 9, 18, 27, 35, 44, 51,
59, 68, 75, 83, 92, 99,
104, 111, 121, 130, 139,
148, 157, 164, 172, 183,
Number
I/O
I
Definition
VCC
193, 201
3.3V power supply.
VSS
8, 17, 26, 34, 43, 52, 60,
67, 76, 84, 91, 98, 103,
112, 120, 129, 138, 147,
156, 163, 171, 177, 184,
192, 200, 208
23:19,16:10,7:2,207:204
24
I
Ground.
LA[21:0]
RESET#
TDMDX
O
I
O
I
Device address output.
Reset.
TDM transmit data output.
ROM Select.
RSEL
0
1
25
RSEL
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS
28
29
30
31
I
I
I
TDM receive data input.
TDM clock input.
TDM frame sync.
TDM output enable.
Audio transmit frame sync output.
System and DSCK output clock frequency selection at reset time. The matrix
below lists the available clock frequencies and their respective PLL bit
settings..
SEL_PLL2
SEL_PLL1
SEL_PLL0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
O
O
32
SEL_PLL1
TSD
SEL_PLL0
SEL_PLL2
33
O
I
I
—
Audio transmit serial data output.
Refer to the description and matrix for SEL_PLL1 pin 32.
Refer to the description and matrix for SEL_PLL1 pin 32.
36
NC
37, 38, 41, 42, 146:142,
155:149, 158, 203:202
39
40
45
46
47
48
No connect. Leave open.
MCLK
TBCK
RSD
RWS
RBCK
APLLCAP
I/O
I/O
I
I
I
I
Audio master clock for audio DAC.
Audio transmit bit clock output.
Audio receive serial data input.
Audio receive frame sync input.
Audio receive bit clock input.
Analog PLL capacitor input.
Selection
16-bit ROM
8-bit ROM
Clock Output
VCO doesn’t work.
27 MHz
Bypass mode
54 MHz
121.5 MHz
81 MHz
94.5 MHz
108 MHz
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