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| 型號： | EPM9320ALI84-10 |
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| 代理商： | EPM9320ALI84-10 |
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Altera Corporation
3
MAX 9000 Programmable Logic Device Family Data Sheet
General
Description
The MAX 9000 family of in-system-programmable, high-density, high-
performance EPLDs is based on Altera’s third-generation MAX
architecture. Fabricated on an advanced CMOS technology, the EEPROM-
based MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin
delays as fast as 10 ns, and counter speeds of up to 144 MHz. The -10 speed
grade of the MAX 9000 family is compliant with the PCI Local Bus
Specification, Revision 2.2
. Table 3 shows the speed grades available for
MAX 9000 devices.
Table 4 shows the performance of MAX 9000 devices for typical functions.
Note:
(1)
Internal logic array block (LAB) performance is shown. Numbers in parentheses show external delays from row
input pin to row I/O pin.
The MAX 9000 architecture supports high-density integration of system-
level logic functions. It easily integrates multiple programmable logic
devices ranging from PALs, GALs, and 22V10s to field-programmable
gate array (FPGA) devices and EPLDs.
Table 3. MAX 9000 Speed Grade Availability
Device
Speed Grade
-10
-15
-20
EPM9320
vv
EPM9320A
v
EPM9400
vv
EPM9480
vv
EPM9560
vv
EPM9560A
v
Table 4. MAX 9000 Performance
Application
Macrocells Used
Speed Grade
Units
-10
-15
-20
16-bit loadable counter
16
144
118
100
MHz
16-bit up/down counter
16
144
118
100
MHz
16-bit prescaled counter
16
144
118
100
MHz
16-bit address decode
1
5.6 (10)
7.9 (15)
10 (20)
ns
16-to-1 multiplexer
1
7.7 (12.1)
10.9 (18)
16 (26)
ns
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