參數資料
型號： EPM7064BTC100-5N
廠商： Altera
文件頁數： 11/66頁
文件大?。?/td> 0K
描述： IC MAX 7000 CPLD 64 100-TQFP
標準包裝： 270
系列： MAX® 7000B
可編程類型： 系統內可編程
最大延遲時間 tpd(1)： 5.0ns
電壓電源 - 內部： 2.375 V ~ 2.625 V
邏輯元件/邏輯塊數目： 4
宏單元數： 64
門數： 1250
輸入/輸出數： 68
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP
供應商設備封裝： 100-TQFP（14x14）
包裝： 托盤
Altera Corporation
19
MAX 7000B Programmable Logic Device Data Sheet
Programming
with External
Hardware
MAX 7000B devices can be programmed on Windows-based PCs with an
Altera Logic Programmer card, the Master Programming Unit (MPU),
and the appropriate device adapter. The MPU performs continuity
checking to ensure adequate electrical contact between the adapter and
the device.
f For more information, see the Altera Programming Hardware Data Sheet.
The Altera software can use text- or waveform-format test vectors created
with the Altera Text Editor or Waveform Editor to test the programmed
device. For added design verification, designers can perform functional
testing to compare the functional device behavior with the results of
simulation.
Data I/O, BP Microsystems, and other programming hardware
manufacturers provide programming support for Altera devices. For
more information, see Programming Hardware Manufacturers.
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
MAX 7000B devices include the JTAG boundary-scan test circuitry
defined by IEEE Std. 1149.1. Table 6 describes the JTAG instructions
supported by MAX 7000B devices. The pin-out tables starting on page 59
of this data sheet show the location of the JTAG control pins for each
device. If the JTAG interface is not required, the JTAG pins are available
as user I/O pins.
Table 6. MAX 7000B JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern output at the device pins.
EXTEST
Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins.
BYPASS
Places the 1-bit bypass register between the TDI and TDO pins, which allows the
boundary-scan test data to pass synchronously through a selected device to adjacent
devices during normal operation.
CLAMP
Allows the values in the boundary-scan register to determine pin states while placing the
1-bit bypass register between the TDI and TDO pins.
IDCODE
Selects the IDCODE register and places it between the TDI and TDO pins, allowing the
IDCODE to be serially shifted out of TDO.
USERCODE
Selects the 32-bit USERCODE register and places it between the TDI and TDO pins,
allowing the USERCODE value to be shifted out of TDO.
ISP Instructions
These instructions are used when programming MAX 7000B devices via the JTAG ports
with the MasterBlaster or ByteBlasterMV download cable, or using a Jam File (.jam),
Jam Byte-Code File (.jbc), or Serial Vector Format File (.svf) via an embedded
processor or test equipment.
相關PDF資料
PDF描述
ACM22DTAN-S664 CONN EDGECARD 44POS R/A .156 SLD
EEC08DRYS CONN EDGECARD 16POS DIP .100 SLD
TAP686M006BRW CAP TANT 68UF 6.3V 20% RADIAL
VI-B4P-CX-B1 CONVERTER MOD DC/DC 13.8V 75W
180-M62-213R031 CONN DB62 FMAL HD SLD DIP NICKEL
相關代理商/技術參數
參數描述
EPM7064BTC100-7 功能描述:CPLD - 復雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7064BTC44-3 功能描述:CPLD - 復雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7064BTC44-3N 功能描述:CPLD - 復雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7064BTC44-5 功能描述:CPLD - 復雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7064BTC44-7 功能描述:CPLD - 復雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數量 廠商 批號 封裝
添加更多采購

我的聯系方式

*
*
*