參數(shù)資料
型號: EPM7032BLC44-3
廠商: Altera
文件頁數(shù): 4/66頁
文件大小: 0K
描述: IC MAX 7000 CPLD 32 44-PLCC
標(biāo)準(zhǔn)包裝: 130
系列: MAX® 7000B
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 3.5ns
電壓電源 - 內(nèi)部: 2.375 V ~ 2.625 V
邏輯元件/邏輯塊數(shù)目: 2
宏單元數(shù): 32
門數(shù): 600
輸入/輸出數(shù): 36
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.58x16.58)
包裝: 管件
12
Altera Corporation
MAX 7000B Programmable Logic Device Data Sheet
Figure 5. MAX 7000B PIA Routing
While the routing delays of channel-based routing schemes in masked or
field-programmable gate arrays (FPGAs) are cumulative, variable, and
path-dependent, the MAX 7000B PIA has a predictable delay. The PIA
makes a design’s timing performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or VCC. Figure 6 shows the I/O
control block for MAX 7000B devices. The I/O control block has
six or ten global output enable signals that are driven by the true or
complement of two output enable signals, a subset of the I/O pins, or a
subset of the I/O macrocells.
To LAB
PIA Signals
相關(guān)PDF資料
PDF描述
PQ015ENA1ZZH IC REG LDO 1.5V 1A SC-63
VI-2TZ-CY-F3 CONVERTER MOD DC/DC 2V 20W
180-M26-203L021 CONN DB26 FMAL HD SLD CUP NICKEL
NDL0512SC CONV DC/DC 2W 5VIN 12VOUT SIP
ECC08DCMH CONN EDGECARD 16POS .100 WW
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM7032BLC44-5 制造商:Rochester Electronics LLC 功能描述: 制造商:Altera Corporation 功能描述:
EPM7032BLC44-7 制造商:Rochester Electronics LLC 功能描述: 制造商:Altera Corporation 功能描述:
EPM7032BTC44-3 制造商:Altera Corporation 功能描述:IC MAX
EPM7032BTC44-3N 制造商:Altera Corporation 功能描述:IC MAX
EPM7032BTC44-5 制造商:Altera Corporation 功能描述:CPLD MAX 7000B Family 600 Gates 32 Macro Cells 212.8MHz CMOS Technology 2.5V 44-Pin TQFP