參數(shù)資料
型號: EPM7032AETI44-7
文件頁數(shù): 12/60頁
文件大?。?/td> 1041K
代理商: EPM7032AETI44-7
2
Altera Corporation
MAX 7000A Programmable Logic Device Data Sheet
...and More
Features
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4.5-ns pin-to-pin logic delays with counter frequencies of up to
227.3 MHz
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MultiVoltTM I/O interface enables device core to run at 3.3 V, while
I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
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Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space-
saving FineLine BGATM, and plastic J-lead chip carrier (PLCC)
packages
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Supports hot-socketing in MAX 7000AE devices
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Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
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PCI-compatible
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Bus-friendly architecture, including programmable slew-rate control
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Open-drain output option
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Programmable macrocell registers with individual clear, preset,
clock, and clock enable controls
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Programmable power-up states for macrocell registers in
MAX 7000AE devices
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Programmable power-saving mode for 50% or greater power
reduction in each macrocell
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Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
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Programmable security bit for protection of proprietary designs
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6 to 10 pin- or logic-driven output enable signals
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Two global clock signals with optional inversion
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Enhanced interconnect resources for improved routability
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Fast input setup times provided by a dedicated path from I/O pin to
macrocell registers
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Programmable output slew-rate control
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Programmable ground pins
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Software design support and automatic place-and-route provided by
Altera’s development systems for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations
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Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, Synplicity, and VeriBest
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Programming support with Altera’s Master Programming Unit
(MPU), MasterBlasterTM serial/universal serial bus (USB)
communications cable, ByteBlasterMVTM parallel port download
cable, and BitBlasterTM serial download cable, as well as
programming hardware from third-party manufacturers and any
JamTM STAPL File (.jam), Jam Byte-Code File (.jbc), or Serial Vector
Format File- (.svf) capable in-circuit tester
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