Note: (1) EPM3032A" />
參數(shù)資料
型號(hào): EPM3512AQI208-10N
廠商: Altera
文件頁(yè)數(shù): 4/46頁(yè)
文件大?。?/td> 0K
描述: IC MAX 3000A CPLD 512 208-PQFP
標(biāo)準(zhǔn)包裝: 72
系列: MAX® 3000A
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 10.0ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目: 32
宏單元數(shù): 512
門(mén)數(shù): 10000
輸入/輸出數(shù): 172
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
包裝: 托盤(pán)
12
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 6. I/O Control Block of MAX 3000A Devices
Note:
(1)
EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have
10 output enables.
When the tri–state buffer control is connected to ground, the output is
tri-stated (high impedance), and the I/O pin can be used as a dedicated
input. When the tri–state buffer control is connected to VCC, the output is
enabled.
The MAX 3000A architecture provides dual I/O feedback, in which
macrocell and pin feedbacks are independent. When an I/O pin is
configured as an input, the associated macrocell can be used for buried
logic.
from
Macrocell
Slew-Rate Control
to PIA
to Other I/O Pins
6 or 10 Global
Output Enable Signals (1)
PIA
VCC
Open-Drain Output
OE Select Multiplexer
GND
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