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| 型號： | EPF8452ALC84-3 |
| 廠商： | Altera |
| 文件頁數(shù)： | 61/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLEX 8000A FPGA 4K 84-PLCC |
| 產(chǎn)品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 75 |
| 系列： | FLEX 8000 |
| LAB/CLB數(shù)： | 42 |
| 邏輯元件/單元數(shù)： | 336 |
| 輸入/輸出數(shù)： | 68 |
| 門數(shù)： | 4000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應商設備封裝： | 84-PLCC（29.31x29.31） |
| 其它名稱： | 544-2256-5 |
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8
Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
The FLEX 8000 architecture provides two dedicated high-speed data
paths—carry chains and cascade chains—that connect adjacent LEs
without using local interconnect paths. The carry chain supports high-
speed counters and adders; the cascade chain implements wide-input
functions with minimum delay. Carry and cascade chains connect all LEs
in an LAB and all LABs in the same row. Heavy use of carry and cascade
chains can reduce routing flexibility. Therefore, the use of carry and
cascade chains should be limited to speed-critical portions of a design.
Carry Chain
The carry chain provides a very fast (less than 1 ns) carry-forward
function between LEs. The carry-in signal from a lower-order bit moves
forward into the higher-order bit via the carry chain, and feeds into both
the LUT and the next portion of the carry chain. This feature allows the
FLEX 8000 architecture to implement high-speed counters and adders of
arbitrary width. The MAX+PLUS II Compiler can create carry chains
automatically during design processing; designers can also insert carry
chain logic manually during design entry.
Figure 4 shows how an n-bit full adder can be implemented in n + 1 LEs
with the carry chain. One portion of the LUT generates the sum of two bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register is typically bypassed for simple adders, but
can be used for an accumulator function. Another portion of the LUT and
the carry chain logic generate the carry-out signal, which is routed directly
to the carry-in signal of the next-higher-order bit. The final carry-out
signal is routed to another LE, where it can be used as a general-purpose
signal. In addition to mathematical functions, carry chain logic supports
very fast counters and comparators.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPF8452ALC844 | 制造商:ALTERA 功能描述:New |
| EPF8452ALC84-4 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 8000 42 LABs 68 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF8452ALC844N | 制造商:Altera Corporation 功能描述:FPGA FLEX 8000 Family 4K Gates 336 Cells 125MHz CMOS Technology 5V 84-Pin PLCC 制造商:Altera 功能描述:FPGA FLEX 8000 Family 4K Gates 336 Cells 125MHz CMOS Technology 5V 84-Pin PLCC |
| EPF8452ALC84-4N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 8000 42 LABs 68 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF8452ALC84-6 | 制造商:Altera Corporation 功能描述:Field-Programmable Gate Array, 336 Cell, 84 Pin, Plastic, PLCC |
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