參數(shù)資料
型號： EPF8282ATC100-3
廠商： Altera
文件頁數(shù)： 7/62頁
文件大小： 0K
描述： IC FLEX 8000A FPGA 2.5K 100-TQFP
產品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 270
系列： FLEX 8000
LAB/CLB數(shù)： 26
邏輯元件/單元數(shù)： 208
輸入/輸出數(shù)： 78
門數(shù)： 2500
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 100-TQFP
供應商設備封裝： 100-TQFP（14x14）
產品目錄頁面： 602 (CN2011-ZH PDF)
其它名稱： 544-2253
Altera Corporation
15
FLEX 8000 Programmable Logic Device Family Data Sheet
FL
EX
800
0
3
Asynchronous Clear
A register is cleared by one of the two LABCTRL signals. When the CLRn
port receives a low signal, the register is set to zero.
Asynchronous Preset
An asynchronous preset is implemented as either an asynchronous load
or an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRLl
asynchronously loads a 1 into the register. Alternatively, the
MAX+PLUS II software can provide preset control by using the clear and
inverting the input and output of the register. Inversion control is
available for the inputs to both LEs and IOEs. Therefore, if a register is
preset by only one of the two LABCTRL signals, the DATA3 input is not
needed and can be used for one of the LE operating modes.
Asynchronous Clear & Preset
When implementing asynchronous clear and preset, LABCTRL1 controls
the preset and LABCTRL2 controls the clear. The DATA3 input is tied to VCC;
therefore, asserting LABCTRL1 asynchronously loads a 1 into the register,
effectively presetting the register. Asserting LABCTRL2 clears the register.
Asynchronous Load with Clear
When implementing an asynchronous load with the clear, LABCTRL1
implements the asynchronous load of DATA3 by controlling the register
preset and clear. LABCTRL2 implements the clear by controlling the
register clear.
Asynchronous Load with Preset
When implementing an asynchronous load in conjunction with a preset,
the MAX+PLUS II software provides preset control by using the clear and
inverting the input and output of the register. Asserting LABCTRL2 clears
the register, while asserting LABCTRL1 loads the register. The
MAX+PLUS II software inverts the signal that drives the DATA3 signal to
account for the inversion of the register’s output.
Asynchronous Load without Clear or Preset
When implementing an asynchronous load without the clear or preset,
LABCTRL1
implements the asynchronous load of DATA3 by controlling the
register preset and clear.
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相關代理商/技術參數(shù)
參數(shù)描述
EPF8282ATC100-3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 8000 26 LABs 78 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF8282ATC1004 制造商:ALTERA 功能描述:*
EPF8282ATC100-4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 8000 26 LABs 78 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF8282ATC100-4N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 8000 26 LABs 78 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF8282ATI100-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 8000 26 LABs 78 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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