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參數(shù)資料
| 型號： | EPCS64SI16N |
| 廠商： | Altera |
| 文件頁數(shù)： | 30/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONFIG DEVICE 64MBIT 16-SOIC |
| 產(chǎn)品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 49 |
| 系列： | EPCS |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 存儲容量： | 64Mb |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 604 (CN2011-ZH PDF) |
| 其它名稱： | 544-1380-5 EPCS64SI16 EPCS64SI16N-ND |
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Page 36
Pin Information
Serial Configuration (EPCS) Devices Datasheet
January 2014
Altera Corporation
Table 23 lists the pin description of the EPCS device.
Figure 23 shows the layout recommendation for vertical migration from the EPCS1
device to the EPCS128 device.
Table 23. EPCS Device Pin Description
Pin
Name
Pin Number
in 8-Pin
SOIC
Package
Pin Number
in 16-Pin
SOIC
Package
Pin Type
Description
DATA
2
8
Output
The DATA output signal transfers data serially out of the EPCS device
to the FPGA during the read operation or configuration. During the
read operation or configuration, the EPCS device is enabled by pulling
the nCS signal low. The DATA signal transitions on the falling edge of
the DCLK signal.
ASDI
5
15
Input
The ASDI signal is used to transfer data serially into the EPCS device.
This pin are also receiving data that are programmed into the EPCS
device. Data is latched on the rising edge of the DCLK signal.
nCS
1
7
Input
The nCS signal toggles at the beginning and the end of a valid
instruction. When this signal goes high, the device is deselected and
the DATA pin is tri-stated. When this signal goes low, the device is
enabled and in an active mode. After power up, the EPCS device
requires a falling edge on the nCS signal before the EPCS device
begins any operation.
DCLK
6
16
Input
The FPGA provides the DCLK signal. This signal provides the timing
for the serial interface. The data presented on the ASDI pin is latched
to the EPCS device on the rising edge of the DCLK signal. The data on
the DATA pin changes after the falling edge of the DCLK signal and is
latched into the FPGA on the next falling edge of the DCLK signal.
VCC
3, 7, 8
1, 2, 9
Power
Connect the power pins to a 3.3-V power supply.
GND
4
10
GND
Ground pin.
Figure 23. Layout Recommendation for Vertical Migration from the EPCS1 Device to the EPCS128
Device
Pi
n1
ID
Pin 1 ID
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EPCSC2.5T | 功能描述:接線端子工具和配件 End Plate RoHS:否 制造商:Phoenix Contact 產(chǎn)品:Tools & Accessories 類型:End Bracket |
| EPCSC2.5T1-2 | 功能描述:接線端子工具和配件 End Plate RoHS:否 制造商:Phoenix Contact 產(chǎn)品:Tools & Accessories 類型:End Bracket |
| EPCSC2.5T2-2 | 功能描述:接線端子工具和配件 End Plate RoHS:否 制造商:Phoenix Contact 產(chǎn)品:Tools & Accessories 類型:End Bracket |
| EPCSC2.5T2-2/BL | 功能描述:接線端子工具和配件 End Plate , Black (50) RoHS:否 制造商:Phoenix Contact 產(chǎn)品:Tools & Accessories 類型:End Bracket |
| EPCSC2.5T2-2/BU | 功能描述:接線端子工具和配件 End Plate , Blue (50) RoHS:否 制造商:Phoenix Contact 產(chǎn)品:Tools & Accessories 類型:End Bracket |
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