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參數(shù)資料
| 型號(hào)： | EPC8QC100N |
| 廠商： | Altera |
| 文件頁數(shù)： | 19/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONFIG DEVICE 8MBIT 100-PQFP |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 系列： | EPC |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 存儲(chǔ)容量： | 8Mb |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-PQFP（14x20） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 604 (CN2011-ZH PDF) |
| 其它名稱： | 544-1683 |
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Page 26
Power Sequencing
Enhanced Configuration (EPC) Devices Datasheet
January 2012
Altera Corporation
Power Sequencing
Altera requires that you power-up the FPGA's VCCINT supply before the EPC device's
POR expires.
Power up needs to be controlled so that the EPC device’s OE signal goes high after the
CONF
_DONE signal is pulled low. If the EPC device exits POR before the FPGA is
powered up, the CONF_DONE signal will be high because the pull-up resistor is holding
this signal high. When the EPC device exits POR, OE is released and pulled high by a
pull-up resistor. Since the EPC device samples the nCS signal on the rising edge of OE,
it detects a high level on CONF_DONE and enters an idle mode. DATA and DCLK outputs
will not toggle in this state and configuration will not begin. The EPC device will only
exit this mode if it is powered down and then powered up correctly.
1 To ensure the EPC device enters configuration mode properly, you must ensure that
the FPGA completes power-up before the EPC device exits POR.
The pin-selectable POR time feature is useful for ensuring this power-up sequence.
The EPC device has two POR settings—2 ms when PORSEL is set to a high level and
100 ms when PORSEL is set to a low level. For more margin, the 100-ms setting can be
selected to allow the FPGA to power-up before configuration is attempted.
Alternatively, a power-monitoring circuit or a power-good signal can be used to keep
the FPGA’s nCONFIG pin asserted low until both supplies have stabilized. This ensures
the correct power up sequence for successful configuration.
Programming and Configuration File Support
The Quartus II software provides programming support for the EPC device and
automatically generates the .pof for the EPC4, EPC8, and EPC16 devices. In a
multi-device project, the Quartus II software can combine the .sof for multiple
ACEX 1K, APEX 20K, APEX II, Cyclone series, FLEX 10K, Mercury, and Stratix series
FPGAs into one programming file for the EPC device.
f For more information about generating programming files, refer to the Altera
EPC devices can be programmed in-system through the industry-standard 4-pin
JTAG interface. The ISP feature in the EPC device provides ease in prototyping and
updating FPGA functionality.
After programming an EPC device in-system, FPGA configuration can be initiated by
including the EPC device’s JTAG INIT_CONF instruction (refer to Table 11).
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