
2–8
Altera Corporation
Stratix II GX Device Handbook, Volume 2
October 2007
Stratix II GX ALT2GXB Ports List
pll_locked
Output
PLL locked indicator for the transmitter PLLs.
Transceiver
block
pll_inclk
Input
Reference clocks for the transmitter PLLs.
Transceiver
block
Calibration Block
cal_blk_clk
Input
Calibration clock for the transceiver termination
blocks. This clock supports frequencies from
10 MHz to 125 MHz.
Device
cal_blk_powerdown
(active_low)
Input
Power-down signal for the calibration block.
Assertion of this signal may interrupt data
transmission and reception. Use this signal to
recalibrate the termination resistors if
temperature and/or voltage changes warrant it.
Device
External Signals
tx_dataout
Output
Transmitter serial output port.
Channel
rx_datain
Input
Receiver serial input port.
Channel
rrefb
Output
Reference resistor port. This port is always
used and must be tied to a 2K-
Ω resistor to
ground. This port is highly sensitive to noise.
There must be no noise coupled to this port.
Device
refclk
Input
Dedicated reference clock inputs (two per
transceiver block) for the transceiver. The
buffer structure is similar to the receiver buffer,
but the termination is not calibrated.
Transceiver
block
gxb_enable
Input
Dedicated transceiver block enable pin. If
instantiated, this port must be tied to the
pll_ena
input pin. A high level on this signal
enables the transceiver block; a low level
disables it.
Transceiver
block
(1)
These are dedicated pins for the transceiver and do not appear in the MegaWizard Plug-In Manager.
Table 2–1. Stratix II GX ALT2GXB Ports (Part 7 of 7)
Port Name
Input/Output
Description
Scope