
2–128
Altera Corporation
Stratix II GX Device Handbook, Volume 2
October 2007
PLD-Transceiver Interface Clocking
The next example is similar to the shared clock example of a tx_clkout
feeding all the RX and TX channels, except that with the 0PPM setting, the
tx_clkout
can drive across transceiver blocks, as shown in
Figure 2–102. The upstream device feeding the RX channels must be
frequency locked to the tx_clkout used.
As with the RX channel example above, it is important to note that
powering down the transceiver block where the driving channel resides
will flatline the tx_clkout. All logic and the write ports of all the TX
phase compensation FIFO will the driving clock feeds will flatline. A
digital reset must be done on all channels after a driving transceiver block
power down event.