2–6
Altera Corporation
Stratix II GX Device Handbook, Volume 1
October 2007
Transceivers
Figure 2–4. Transmitter PLL Block Note (1) (1)
The global clock line must be driven by an input pin.
The transmitter PLLs support data rates up to 6.375 Gbps. The input clock
frequency is limited to 622.08 MHz. An optional pll_locked port is
available to indicate whether the transmitter PLL is locked to the
reference clock. Both transmitter PLLs have a programmable loop
bandwidth parameter that can be set to low, medium, or high. The loop
bandwidth parameter can be statically set in the Quartus II software.
Table 2–2 lists the adjustable parameters in the transmitter PLL.
PFD
Dedicated Local
REFCLK 0
CP+LF
up
dn
VCO
From PLD
Inter-Transceiver Block
Routing (IQ[4:0])
From PLD
Inter-Transceiver Block
Routing (IQ[4:0])
L
PFD
Dedicated Local
REFCLK 1
CP+LF
up
dn
VCO
m
2
INCLK
L
Transmitter PLL 1
Transmitter PLL 0
High-Speed
Transmitter PLL0 Clock
High-Speed
Transmitter PLL1 Clock
High-Speed
Transmitter PLL Clock
To Inter-Transceiver
Block Line
/2
2
÷
m
÷
INCLK
Table 2–2. Transmitter PLL Specifications
Parameter
Specifications
Input reference frequency range
50 MHz to 622.08 MHz
Data rate support
600 Mbps to 6.375 Gbps
Multiplication factor (W)
1, 4, 5, 8, 10, 16, 20, 25
Bandwidth
Low, medium, or high