
3–64
Altera Corporation
Stratix II GX Device Handbook, Volume 2
October 2007
Channel and PMA Controls Reconfiguration
The following signals are used in 32-bit SONET/SDH scrambled backplane
mode:
Four Control Data Bits (rx_dataout)
rx_dataoutfull[7:0]
- rx_dataout (LSByte)
rx_dataoutfull[23:16]
rx_dataoutfull[39:32]
rx_dataoutfull
[55:48]
- rx_dataout (MSByte)
rx_dataoutfull[8]
, rx_dataoutfull[24],
rx_dataoutfull[40]
, and rx_dataoutfull[56]: four Reserved
Four Receiver Sync Status Bits
rx_dataoutfull[10]
- rx_syncstatus (LSB)
rx_dataoutfull[26]
rx_dataoutfull[42]
rx_dataoutfull[58]
- rx_syncstatus (MSB)
Four Receiver Pattern Detect Bits
rx_dataoutfull[12]
- rx_patterndetect (LSB)
rx_dataoutfull[28]
rx_dataoutfull[44]
rx_dataoutfull[60]
- rx_patterndetect (MSB)
40-bit mode
Four 10-bit Control Data Bits (rx_dataout)
rx_dataoutfull[9:0]
- rx_dataout (LSByte)
rx_dataoutfull[25:16]
rx_dataoutfull[41:32]
rx_dataoutfull[57:48]
- rx_dataout (MSByte)
Four Receiver Sync Status Bits
rx_dataoutfull[10]
- rx_syncstatus (LSB)
rx_dataoutfull[26]
rx_dataoutfull[42]
rx_dataoutfull[58]
- rx_syncstatus (MSB)
Four Receiver Pattern Detect Bits
rx_dataoutfull[12]
- rx_patterndetect (LSB)
rx_dataoutfull[28]
rx_dataoutfull[44]
rx_dataoutfull[60]
- rx_patterndetect (MSB)
PLD Interface Description
Receive Signal Description
(Based on Stratix II GX Supported PLD Interface Widths)