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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP2S60F672I4
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 515/768闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC STRATIX II FPGA 60K 672-FBGA
鐢㈠搧鍩硅〒妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯欐簴鍖呰锛� 10
绯诲垪锛� Stratix® II
LAB/CLB鏁�(sh霉)锛� 3022
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 60440
RAM 浣嶇附瑷堬細 2544192
杓稿叆/杓稿嚭鏁�(sh霉)锛� 492
闆绘簮闆诲锛� 1.15 V ~ 1.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 100°C
灏佽/澶栨锛� 672-BBGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 672-BGA锛�27x27锛�
閰嶇敤锛� 544-1700-ND - DSP KIT W/STRATIX II EP2S60N
544-1697-ND - NIOS II KIT W/STRATIX II EP2S60N
鍏跺畠鍚嶇ū锛� 544-1915
EP2S60F672I4-ND
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7鈥�10
Altera Corporation
Stratix II Device Handbook, Volume 2
January 2008
Configuration Features
VCCPD Pins
Stratix II and Stratix II GX devices also offer a new power supply, VCCPD,
which must be connected to 3.3-V in order to power the 3.3-V/2.5-V
buffer available on the configuration input pins and JTAG pins. VCCPD
applies to all the JTAG input pins (TCK, TMS, TDI, and TRST) and the
configuration pins when VCCSEL is connected to ground. Refer to
Table 7鈥�5 for information on the pins affected by VCCSEL.
1
VCCPD must ramp-up from 0-V to 3.3-V within 100 ms. If VCCPD
is not ramped up within this specified time, your Stratix II or
Stratix II GX device will not configure successfully. If your
system does not allow for a VCCPD ramp-up time of 100 ms or
less, you must hold nCONFIG low until all power supplies are
stable.
VCCSEL Pin
The VCCSEL pin selects the type of input buffer used on configuration
input pins and it selects the POR trip point voltage level for VCCIO bank 3
powered by VCCIO3 pins.
1
For more information, refer to Table 7鈥�24 on page 7鈥�105.
The configuration input pins and the PLL_ENA pin (Table 7鈥�5) have a
dual buffer design. These pins have a 3.3-V/2.5-V input buffer and a
1.8-V/1.5-V input buffer. The VCCSEL input pin selects which input
buffer is used during configuration. The 3.3-V/2.5-V input buffer is
powered by VCCPD, while the 1.8-V/1.5-V input buffer is powered by
VCCIO. After configuration, the dual-purpose configuration pins are
powered by the VCCIO pins of the bank in which they reside. Table 7鈥�5
shows the pins affected by VCCSEL.
鐩搁棞PDF璩囨枡
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