Altera Corporation
4–23
January 2008
Stratix II Device Handbook, Volume 2
Selectable I/O Standards in Stratix II and Stratix II GX Devices
SSTL-18 Class I
v
SSTL-18 Class II
vv
v
1.8-V HSTL Class I
vv
v
vv
v
1.8-V HSTL Class II
v
v
1.5-V HSTL Class I
vv
v
vv
v
1.5-V HSTL Class II
v
v
1.2-V HSTL
vv
v
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
1.8-V differential HSTL Class I
1.8-V differential HSTL Class II
1.5-V differential HSTL Class I
1.5-V differential HSTL Class II
LVDS
v
v
vv
v
HyperTransport technology
v
Differential LVPECL
vv
v
(1)
This bank is not available in Stratix II GX Devices.
(2)
A mixture of single-ended and differential I/O standards is not allowed in enhanced PLL external clock output
bank.
(3)
This I/O standard is only supported for the input operation in this I/O bank.
(4)
Although the Quartus II software does not support pseudo-differential SSTL/HSTL I/O standards on the left and
(5)
This I/O standard is supported for both input and output operations for pins that support the DQS function. Refer
(6)
This I/O standard is only supported for the input operation for pins that support PLL INCLK function in this I/O
bank.
Table 4–2. Stratix II and Stratix II GX Regular I/O Standards Support (Part 2 of 2)
I/O Standard
General I/O Bank
Enhanced PLL External
Clock Output Bank (2)
12
3
4
5(1) 6(1)
78
9
10
11
12