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參數(shù)資料
| 型號： | EP2S130F1020C4 |
| 廠商： | Altera |
| 文件頁數(shù)： | 636/768頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX II FPGA 130K 1020FBGA |
| 產(chǎn)品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 6 |
| 系列： | Stratix® II |
| LAB/CLB數(shù)： | 6627 |
| 邏輯元件/單元數(shù)： | 132540 |
| RAM 位總計： | 6747840 |
| 輸入/輸出數(shù)： | 742 |
| 電源電壓： | 1.15 V ~ 1.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 1020-BBGA |
| 供應商設(shè)備封裝： | 1020-FBGA（33x33） |
| 其它名稱： | 544-1413 |
Altera Corporation
8–11
January 2008
Stratix II Device Handbook, Volume 2
Remote System Upgrades with Stratix II and Stratix II GX Devices
After power up or a configuration error, the factory configuration logic
should write the remote system upgrade control register to specify the
page address of the application configuration to be loaded. The factory
configuration should also specify whether or not to enable the user
watchdog timer for the application configuration and, if enabled, specify
the timer setting.
The user watchdog timer ensures that the application configuration is
valid and functional. After confirming the system is healthy, the
user-designed application configuration should reset the timer
periodically during user-mode operation of an application configuration.
This timer reset logic should be a user-designed hardware and/or
software health monitoring signal that indicates error-free system
operation. If the user application configuration detects a functional
problem or if the system hangs, the timer is not reset in time and the
dedicated circuitry updates the remote system upgrade status register,
triggering the device to load the factory configuration. The user
watchdog timer is automatically disabled for factory configurations.
1
Only valid application configurations designed for remote
update mode include the logic to reset the timer in user mode.
1
For more information about the user watchdog timer, see “User
If there is an error while loading the application configuration, the remote
system upgrade status register is written by the Stratix II or Stratix II GX
FPGA’s dedicated remote system upgrade circuitry, specifying the cause
of the reconfiguration. Actions that cause the remote system upgrade
status register to be written are:
■
nSTATUS
driven low externally
■
Internal CRC error
■
User watchdog timer time out
■
A configuration reset (logic array nCONFIG signal or external
nCONFIG
pin assertion)
Stratix II and Stratix II GX FPGAs automatically load the factory
configuration located at page address zero. This user-designed factory
configuration should read the remote system upgrade status register to
determine the reason for reconfiguration. The factory configuration
should then take appropriate error recovery steps and write to the remote
system upgrade control register to determine the next application
configuration to be loaded.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP2S130F1020C4N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II 6627 LABs 742 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S130F1020C4RB | 制造商:Altera Corporation 功能描述:FPGA Stratix |
| EP2S130F1020C5 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II 6627 LABs 742 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S130F1020C5N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II 6627 LABs 742 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S130F1020I4 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II 6627 LABs 742 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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