參數(shù)資料
型號: EP20K60ETI144-1ES
英文描述: FPGA
中文描述: FPGA的
文件頁數(shù): 88/114頁
文件大?。?/td> 1623K
代理商: EP20K60ETI144-1ES
Altera Corporation
75
APEX 20K Programmable Logic Device Family Data Sheet
Figure 40. Synchronous Bidirectional Pin External Timing
Notes:
(1)
The output enable and input registers are LE registers in the LAB adjacent to a bi-
directional row pin. The output enable register is set with “Output Enable Routing=
Signal-Pin” option in the Quartus II software.
(2)
The LAB adjacent input register is set with “Decrease Input Delay to Internal Cells=
Off”. This maintains a zero hold time for lab adjacent registers while giving a fast,
position independent setup time. A faster setup time with zero hold time is possible
by setting “Decrease Input Delay to Internal Cells= ON” and moving the input
register farther away from the bi-directional pin. The exact position where zero
hold occurs with the minimum setup time, varies with device density and speed
grade.
Table 35 describes the fMAX timing parameters shown in Figure 36.
PRN
CLRN
DQ
PRN
CLRN
DQ
(1)
IOE Register
Bidirectional Pin
Dedicated
Clock
PRN
CLRN
DQ
(1)
XZBIDIR
t
ZXBIDIR
t
OUTCOBIDIR
t
INSUBIDIR
t
INHBIDIR
t
OE Register
Output IOE Register
Input Register
(2)
Table 35. APEX 20K fMAX Timing Parameters
(Part 1 of 2)
Symbol
Parameter
tSU
LE register setup time before clock
tH
LE register hold time after clock
tCO
LE register clock-to-output delay
tLUT
LUT delay for data-in
tESBRC
ESB Asynchronous read cycle time
tESBWC
ESB Asynchronous write cycle time
tESBWESU
ESB WE setup time before clock when using input register
tESBDATASU
ESB data setup time before clock when using input register
tESBADDRSU
ESB address setup time before clock when using input registers
tESBDATACO1
ESB clock-to-output delay when using output registers
tESBDATACO2
ESB clock-to-output delay without output registers
相關(guān)PDF資料
PDF描述
EP20K60ETI144-2ES FPGA
EP20K60ETI144-3ES Dual Voltage Monitor with Intergrated CPU Supervisor
EP20K100ERI208-1ES Single Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 8-MSOP
EP20K100ERI208-2ES Single Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 8-MSOP
EP20K100ERI208-3ES FPGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K60ETI144-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ETI144-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP2101-7R 制造商:Power-One 功能描述:DC/DC PS DUAL-OUT 3.3V/5.1V 20A/18A 91W 15PIN - Bulk
EP2101-9R 功能描述:EURO-CASSETTE 110W 3.3V + 5.1V RoHS:否 類別:電源 - 外部/內(nèi)部(非板載) >> DC DC Converters 系列:* 標(biāo)準(zhǔn)包裝:1 系列:Quint 類型:隔離 輸入電壓:24V 輸出:24V 輸出數(shù):1 輸出 - 1 @ 電流(最大):24 VDC @ 50A 輸出 - 2 @ 電流(最大):- 輸出 - 3 @ 電流(最大):- 輸出 - 4 @ 電流(最大):- 功率(瓦特):1200W 安裝類型:底座安裝 工作溫度:0°C ~ 40°C 效率:- 封裝/外殼:模塊 尺寸/尺寸:4.33" L x 9.09" W x 6.14" H(110mm x 231mm x 156mm) 包裝:散裝 電源(瓦特)- 最大:1200W 批準(zhǔn):- 其它名稱:277-69722866365-NDQUINT-BAT/24DC/12AH
EP21-6.9KOHMS.1PCT 制造商: 功能描述: 制造商:undefined 功能描述: