參數(shù)資料
型號: EP20K100FC324-3
英文描述: Monolithic 1A Step-Down Regulator with Low Quiescent Current; Temperature Range: -40°C to 85°C; Package: 10-MSOP
中文描述: 現(xiàn)場可編程門陣列(FPGA)
文件頁數(shù): 64/114頁
文件大小: 1623K
代理商: EP20K100FC324-3
Altera Corporation
53
APEX 20K Programmable Logic Device Family Data Sheet
Tables 17 and 18 summarize the ClockLock and ClockBoost parameters
for APEX 20KE devices.
Table 17. APEX 20KE ClockLock & ClockBoost Parameters
Symbol
Parameter
Condition
Min
Typ
Max
Unit
tR
Input rise time
5ns
tF
Input fall time
5ns
tINDUTY
Input duty cycle
40
60
%
tINJITTER
Input jitter peak-to-peak
2
% of input
period
peak-to-
peak
tOUTJITTER Jitter on ClockLock or ClockBoost-
generated clock
0.35
% of
output period
RMS
tOUTDUTY
Duty cycle for ClockLock or
ClockBoost-generated clock
45
55
%
tLOCK (2),
Time required for ClockLock or
ClockBoost to acquire lock
40
s
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