參數(shù)資料
型號(hào): EP20K100EQC240-1
廠商: Altera
文件頁數(shù): 89/117頁
文件大?。?/td> 0K
描述: IC APEX 20KE FPGA 100K 240-PQFP
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 24
系列: APEX-20K®
LAB/CLB數(shù): 416
邏輯元件/單元數(shù): 4160
RAM 位總計(jì): 53248
輸入/輸出數(shù): 183
門數(shù): 263000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 240-BFQFP
供應(yīng)商設(shè)備封裝: 240-PQFP(32x32)
其它名稱: 544-1863
EP20K100EQC240-1-ND
Altera Corporation
73
APEX 20K Programmable Logic Device Family Data Sheet
Tables 32 and 33 describe APEX 20K external timing parameters.
tESBDATACO2
ESB clock-to-output delay without output registers
tESBDD
ESB data-in to data-out delay for RAM mode
tPD
ESB macrocell input to non-registered output
tPTERMSU
ESB macrocell register setup time before clock
tPTERMCO
ESB macrocell register clock-to-output delay
tF1-4
Fanout delay using local interconnect
tF5-20
Fanout delay using MegaLab Interconnect
tF20+
Fanout delay using FastTrack Interconnect
tCH
Minimum clock high time from clock pin
tCL
Minimum clock low time from clock pin
tCLRP
LE clear pulse width
tPREP
LE preset pulse width
tESBCH
Clock high time
tESBCL
Clock low time
tESBWP
Write pulse width
tESBRP
Read pulse width
Table 31. APEX 20K fMAX Timing Parameters
(Part 2 of 2)
Symbol
Parameter
Table 32. APEX 20K External Timing Parameters
Symbol
Clock Parameter
tINSU
Setup time with global clock at IOE register
tINH
Hold time with global clock at IOE register
tOUTCO
Clock-to-output delay with global clock at IOE register
Table 33. APEX 20K External Bidirectional Timing Parameters
Symbol
Parameter
Conditions
tINSUBIDIR
Setup time for bidirectional pins with global clock at same-row or same-
column LE register
tINHBIDIR
Hold time for bidirectional pins with global clock at same-row or same-
column LE register
tOUTCOBIDIR
Clock-to-output delay for bidirectional pins with global clock at IOE
register
C1 = 10 pF
tXZBIDIR
Synchronous IOE output buffer disable delay
C1 = 10 pF
tZXBIDIR
Synchronous IOE output buffer enable delay, slow slew rate = off
C1 = 10 pF
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EP20K100EQC240-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100EQC240-1N 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 183 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100EQC240-1X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 183 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100EQC240-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 183 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100EQC240-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA