參數(shù)資料
型號： EP1SGX40DF1020C6
廠商： Altera
文件頁數(shù)： 172/1456頁
文件大?。?/td> 0K
描述： IC STRATIX GX FPGA 40K 1020-FBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 12
系列： Stratix® GX
LAB/CLB數(shù)： 4125
邏輯元件/單元數(shù)： 41250
RAM 位總計： 3423744
輸入/輸出數(shù)： 624
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 1020-BBGA
供應(yīng)商設(shè)備封裝： 1020-FBGA（33x33）
19–4
Altera Corporation
Stratix GX Device Handbook, Volume 2
September 2004
TriMatrix Memory Overview
Each DSP block supports either eight 9
× 9-bit multipliers, four 18-bit
multipliers, or one 36
× 36-bit multiplier. These multipliers can feed an
adder or an accumulator unit based on the operation mode. Table 19–3
shows the different operation modes for the DSP blocks.
Implementing multipliers, multiply-adders, and multiply-accumulators
in the DSP blocks has a performance advantage over logic cell
implementation. Using DSP blocks also reduces logic cell and routing
resource consumption. To achieve higher performance, register each
stage of the DSP block to allow pipelining. For implementing
applications, such as FIR filters, efficiently use the input registers of the
DSP block as shift registers.
f
For more information on DSP blocks, see the DSP Blocks in Stratix &
Stratix GX Devices chapter.
TriMatrix
Memory
Overview
Stratix and Stratix GX devices feature the TriMatrix memory structure,
composed of three sizes of embedded RAM blocks. These include the
512-bit size M512 block, the 4-Kbit size M4K block, and the 512-Kbit size
M-RAM block. Each block is configurable to support a wide range of
features.
Tables 19–4 and 19–5 show the number of memory blocks in each Stratix
and Stratix GX device, respectively.
Table 19–3. Operation Modes for DSP Blocks
DSP Block Mode
Number & Size of Multipliers per DSP Block
9 x 9-bit
18 x 18-bit
36 x 36-bit
Simple multiplier
Eight multipliers with
eight product outputs
Four multipliers with four
product outputs
One multiplier with one
product output
Multiply-accumulate
Two multiply and
accumulate (34 bit)
Two multiply and
accumulate (52 bit)
Two-multipliers adder
4 two-multipliers adders
2 two-multipliers adders
Four-multipliers adder
2 four-multipliers adder
1 four-multipliers adder
Table 19–4. TriMatrix Memory Resources in Stratix Devices (Part 1 of 2)
Device
M512
M4K
M-RAM
EP1S10
94
60
1
EP1S20
194
82
2
EP1S25
224
138
2
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1SGX40DF1020C6N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix I GX 4125 LABs 624 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1SGX40DF1020C7 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix I GX 4125 LABs 624 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1SGX40DF1020C7N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix I GX 4125 LABs 624 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1SGX40DF1020I6N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix I GX 4125 LABs 624 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1SGX40G 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:StratixGX FPGA Family
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