參數(shù)資料
型號(hào): EP1K50TI144-1DX
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 現(xiàn)場(chǎng)可編程門(mén)陣列(FPGA)
文件頁(yè)數(shù): 81/86頁(yè)
文件大?。?/td> 1263K
代理商: EP1K50TI144-1DX
82
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
The ICCACTIVE value can be calculated with the following equation:
ICCACTIVE = K × fMAX × N × togLC (A)
Where:
fMAX
=
Maximum operating frequency in MHz
N
=
Total number of LEs used in the device
togLC
=
Average percent of LEs toggling at each clock
(typically 12.5%)
K
=
Constant
Table 58 provides the constant (K) values for ACEX 1K devices.
This supply power calculation provides an ICC estimate based on typical
conditions with no output load. The actual ICC should be verified during
operation because this measurement is sensitive to the actual pattern in
the device and the environmental operating conditions.
To better reflect actual designs, the power model (and the constant K in
the power calculation equations) for continuous interconnect ACEX 1K
devices assumes that LEs drive FastTrack Interconnect channels. In
contrast, the power model of segmented FPGAs assumes that all LEs
drive only one short interconnect segment. This assumption may lead to
inaccurate results when compared to measured power consumption for
actual designs in segmented FPGAs.
Figure 31 shows the relationship between the current and operating
frequency of ACEX 1K devices. For information on other ACEX 1K
devices, contact Altera Applications at (800) 800-EPLD.
Table 58. ACEX 1K Constant Values
Device
K Value
EP1K10
4.5
EP1K30
4.5
EP1K50
4.5
EP1K100
4.5
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