參數(shù)資料
型號(hào)： EP1K50FI484-1DX
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 現(xiàn)場(chǎng)可編程門(mén)陣列（FPGA）
文件頁(yè)數(shù)： 54/86頁(yè)
文件大?。?/td> 1263K
代理商： EP1K50FI484-1DX
58
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
Microparameters are timing delays contributed by individual architectural elements. These parameters cannot be
measured explicitly.
(2)
Operating conditions: VCCIO = 3.3 V ± 10% for commercial or industrial use in ACEX 1K devices
(3)
Operating conditions: VCCIO = 2.5 V ± 5% for commercial or industrial use in ACEX 1K devices.
(4)
Operating conditions: VCCIO = 2.5 V or 3.3 V.
(5)
Because the RAM in the EAB is self-timed, this parameter can be ignored when the WE signal is registered.
(6)
EAB macroparameters are internal parameters that can simplify predicting the behavior of an EAB at its boundary;
these parameters are calculated by summing selected microparameters.
(7)
These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing
analysis are required to determine actual worst-case performance.
Table 26. Interconnect Timing Microparameters
Symbol
Parameter
Conditions
tDIN2IOE
Delay from dedicated input pin to IOE control input
tDIN2LE
Delay from dedicated input pin to LE or EAB control input
tDIN2DATA
Delay from dedicated input or clock to LE or EAB data
tDCLK2IOE
Delay from dedicated clock pin to IOE clock
tDCLK2LE
Delay from dedicated clock pin to LE or EAB clock
tSAMELAB
Routing delay for an LE driving another LE in the same LAB
tSAMEROW
Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the
same row
tSAMECOLUMN
Routing delay for an LE driving an IOE in the same column
tDIFFROW
Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different
row
tTWOROWS
Routing delay for a row IOE or EAB driving an LE or EAB in a different row
tLEPERIPH
Routing delay for an LE driving a control signal of an IOE via the peripheral
control bus
tLABCARRY
Routing delay for the carry-out signal of an LE driving the carry-in signal of a
different LE in a different LAB
tLABCASC
Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1K50FI484-1F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI484-1P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI484-1X 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI484-2 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述:
EP1K50FI484-2DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
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