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參數(shù)資料
| 型號： | EP1K50FI256-3F |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場可編程門陣列（FPGA） |
| 文件頁數(shù)： | 36/86頁 |
| 文件大?。?/td> | 1263K |
| 代理商： | EP1K50FI256-3F |
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Altera Corporation
41
ACEX 1K Programmable Logic Device Family Data Sheet
Development
13
Tools
The VCCINT pins must always be connected to a 2.5-V power supply. With
a 2.5-V VCCINT level, input voltages are compatible with 2.5-V, 3.3-V, and
5.0-V inputs. The VCCIO pins can be connected to either a 2.5-V or 3.3-V
power supply, depending on the output requirements. When the VCCIO
pins are connected to a 2.5-V power supply, the output levels are
compatible with 2.5-V systems. When the VCCIO pins are connected to a
3.3-V power supply, the output high is at 3.3 V and is therefore compatible
with 3.3-V or 5.0-V systems. Devices operating with VCCIO levels higher
than 3.0 V achieve a faster timing delay of tOD2 instead of tOD1.
Table 13 summarizes ACEX 1K MultiVolt I/O support.
Notes:
(1)
The PCI clamping diode must be disabled on an input which is driven with a
voltage higher than VCCIO.
(2)
When VCCIO = 3.3 V, an ACEX 1K device can drive a 2.5-V device that has 3.3-V
tolerant inputs.
Open-drain output pins on ACEX 1K devices (with a pull-up resistor to
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a higher
VIH than LVTTL. When the open-drain pin is active, it will drive low.
When the pin is inactive, the resistor will pull up the trace to 5.0 V, thereby
meeting the CMOS VOH requirement. The open-drain pin will only drive
low or tri-state; it will never drive high. The rise time is dependent on the
value of the pull-up resistor and load impedance. The IOL current
specification should be considered when selecting a pull-up resistor.
Power
Sequencing &
Hot-Socketing
Because ACEX 1K devices can be used in a mixed-voltage environment,
they have been designed specifically to tolerate any possible power-up
sequence. The VCCIO and VCCINT power planes can be powered in any
order.
Signals can be driven into ACEX 1K devices before and during power up
without damaging the device. Additionally, ACEX 1K devices do not
drive out during power up. Once operating conditions are reached,
ACEX 1K devices operate as specified by the user.
Table 13. ACEX 1K MultiVolt I/O Support
VCCIO (V)
Input Signal (V)
Output Signal (V)
2.5
3.3
5.0
2.5
3.3
5.0
2.5
v
v
3.3
vv
v (1)
v (2)
vv
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP1K50FI484-1DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI484-1F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI484-1P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI484-1X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI484-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述: |
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