參數(shù)資料
型號: EP1K10TC144-1
廠商: Altera
文件頁數(shù): 7/86頁
文件大?。?/td> 0K
描述: IC ACEX 1K FPGA 10K 144-TQFP
產品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 180
系列: ACEX-1K®
LAB/CLB數(shù): 72
邏輯元件/單元數(shù): 576
RAM 位總計: 12288
輸入/輸出數(shù): 92
門數(shù): 56000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 144-LQFP
供應商設備封裝: 144-TQFP(20x20)
Altera Corporation
15
ACEX 1K Programmable Logic Device Family Data Sheet
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Each LAB provides four control signals with programmable inversion
that can be used in all eight LEs. Two of these signals can be used as clocks,
the other two can be used for clear/preset control. The LAB clocks can be
driven by the dedicated clock input pins, global signals, I/O signals, or
internal signals via the LAB local interconnect. The LAB preset and clear
control signals can be driven by the global signals, I/O signals, or internal
signals via the LAB local interconnect. The global control signals are
typically used for global clock, clear, or preset signals because they
provide asynchronous control with very low skew across the device. If
logic is required on a control signal, it can be generated in one or more LEs
in any LAB and driven into the local interconnect of the target LAB. In
addition, the global control signals can be generated from LE outputs.
Logic Element
The LE, the smallest unit of logic in the ACEX 1K architecture, has a
compact size that provides efficient logic utilization. Each LE contains a
4-input LUT, which is a function generator that can quickly compute any
function of four variables. In addition, each LE contains a programmable
flipflop with a synchronous clock enable, a carry chain, and a cascade
chain. Each LE drives both the local and the FastTrack Interconnect
routing structure. Figure 8 shows the ACEX 1K LE.
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相關代理商/技術參數(shù)
參數(shù)描述
EP1K10TC144-1N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 72 LABs 92 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K10TC144-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 72 LABs 92 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K10TC144-2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 72 LABs 92 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K10TC144-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 72 LABs 92 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K10TC144-3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 72 LABs 92 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256