參數資料
型號： EP1K10TC144-1
廠商： Altera
文件頁數： 26/86頁
文件大?。?/td> 0K
描述： IC ACEX 1K FPGA 10K 144-TQFP
產品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 180
系列： ACEX-1K®
LAB/CLB數： 72
邏輯元件/單元數： 576
RAM 位總計： 12288
輸入/輸出數： 92
門數： 56000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 144-LQFP
供應商設備封裝： 144-TQFP（20x20）
32
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
When dedicated inputs drive non-inverted and inverted peripheral clears,
clock enables, and output enables, two signals on the peripheral control
bus will be used.
Table 7 lists the sources for each peripheral control signal and shows how
the output enable, clock enable, clock, and clear signals share
12 peripheral control signals. Table 7 also shows the rows that can drive
global signals.
Signals on the peripheral control bus can also drive the four global signals,
referred to as GLOBAL0 through GLOBAL3. An internally generated signal
can drive a global signal, providing the same low-skew, low-delay
characteristics as a signal driven by an input pin. An LE drives the global
signal by driving a row line that drives the peripheral bus which then
drives the global signal. This feature is ideal for internally generated clear
or clock signals with high fan-out. However, internally driven global
signals offer no advantage over the general-purpose interconnect for
routing data signals.
The chip-wide output enable pin is an active-high pin that can be used to
tri-state all pins on the device. This option can be set in the Altera
software. The built-in I/O pin pull-up resistors (which are active during
configuration) are active when the chip-wide output enable pin is
asserted. The registers in the IOE can also be reset by the chip-wide reset
pin.
Table 7. Peripheral Bus Sources for ACEX Devices
Peripheral Control Signal
EP1K10
EP1K30
EP1K50
EP1K100
OE0
Row ARow ARow ARow A
OE1
Row A
Row B
Row C
OE2
Row B
Row C
Row D
Row E
OE3
Row B
Row D
Row F
Row L
OE4
Row C
Row E
Row H
Row I
OE5
Row C
Row F
Row J
Row K
CLKENA0
/CLK0/GLOBAL0
Row A
Row F
CLKENA1
/OE6/GLOBAL1
Row A
Row B
Row C
Row D
CLKENA2
/CLR0
Row B
Row C
Row E
Row B
CLKENA3
/OE7/GLOBAL2
Row B
Row D
Row G
Row H
CLKENA4
/CLR1
Row C
Row E
Row I
Row J
CLKENA5
/CLK1/GLOBAL3
Row C
Row F
Row J
Row G
相關PDF資料
PDF描述
AYM30DTMS-S189 CONN EDGECARD 60POS R/A .156 SLD
EP1K10TC144-1N IC ACEX 1K FPGA 10K 144-TQFP
ASM30DTMS-S189 CONN EDGECARD 60POS R/A .156 SLD
M1A3P250-1VQG100I IC FPGA 1KB FLASH 250K 100-VQFP
ACM36DTMS-S189 CONN EDGECARD 72POS R/A .156 SLD
相關代理商/技術參數
參數描述
EP1K10TC144-1N 功能描述:FPGA - 現場可編程門陣列 FPGA - ACEX 1K 72 LABs 92 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K10TC144-2 功能描述:FPGA - 現場可編程門陣列 FPGA - ACEX 1K 72 LABs 92 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K10TC144-2N 功能描述:FPGA - 現場可編程門陣列 FPGA - ACEX 1K 72 LABs 92 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K10TC144-3 功能描述:FPGA - 現場可編程門陣列 FPGA - ACEX 1K 72 LABs 92 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K10TC144-3N 功能描述:FPGA - 現場可編程門陣列 FPGA - ACEX 1K 72 LABs 92 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數量 廠商 批號 封裝
添加更多采購

我的聯系方式

*
*
*