鍨嬭櫉(h脿o)锛� | EP1K10FC256-3 |
寤犲晢锛� | Altera |
鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 68/86闋�(y猫) |
鏂囦欢澶у皬锛� | 0K |
鎻忚堪锛� | IC ACEX 1K FPGA 10K 256-FBGA |
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Three Reasons to Use FPGA's in Industrial Designs |
妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
绯诲垪锛� | ACEX-1K® |
LAB/CLB鏁�(sh霉)锛� | 72 |
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 576 |
RAM 浣嶇附瑷�(j矛)锛� | 12288 |
杓稿叆/杓稿嚭鏁�(sh霉)锛� | 136 |
闁€(m茅n)鏁�(sh霉)锛� | 56000 |
闆绘簮闆诲锛� | 2.375 V ~ 2.625 V |
瀹夎椤�(l猫i)鍨嬶細 | 琛ㄩ潰璨艰 |
宸ヤ綔婧害锛� | 0°C ~ 70°C |
灏佽/澶栨锛� | 256-BGA |
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 256-FBGA锛�17x17锛� |
鍏跺畠鍚嶇ū锛� | 544-1026 |
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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AGL060V2-CS121I | IC FPGA 1KB FLASH 60K 121-CSP |
ABB66DHFR-S621 | EDGECARD 132PS .050 SMD W/O POST |
AGL060V2-CSG121I | IC FPGA 1KB FLASH 60K 121-CSP |
AGLN060V2-VQG100I | IC FPGA NANO 1KB 60K 100VQFP |
ACB66DHFR-S578 | EDGECARD 132POS .050 SMD W/POSTS |
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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EP1K10FC256-3N | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪 FPGA - ACEX 1K 72 LABs 136 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP1K10FI256-2 | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪 FPGA - ACEX 1K 72 LABs 136 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP1K10FI256-2N | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪 FPGA - ACEX 1K 72 LABs 136 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP1K10QC208-1 | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪 FPGA - ACEX 1K 72 LABs 120 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP1K10QC208-1N | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪 FPGA - ACEX 1K 72 LABs 120 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |