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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | EP1K10FC256-3 |
| 寤犲晢锛� | Altera |
| 鏂囦欢闋佹暩(sh霉)锛� | 62/86闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC ACEX 1K FPGA 10K 256-FBGA |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Three Reasons to Use FPGA's in Industrial Designs |
| 妯欐簴鍖呰锛� | 90 |
| 绯诲垪锛� | ACEX-1K® |
| LAB/CLB鏁�(sh霉)锛� | 72 |
| 閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 576 |
| RAM 浣嶇附瑷堬細 | 12288 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 136 |
| 闁€鏁�(sh霉)锛� | 56000 |
| 闆绘簮闆诲锛� | 2.375 V ~ 2.625 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 256-BGA |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 256-FBGA锛�17x17锛� |
| 鍏跺畠鍚嶇ū锛� | 544-1026 |
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Altera Corporation
65
ACEX 1K Programmable Logic Device Family Data Sheet
D
e
ve
lo
pm
e
n
t
13
To
o
ls
Notes to tables:
(1)
(2)
This parameter is measured without the use of the ClockLock or ClockBoost circuits.
(3)
These parameters are specified by characterization.
(4)
This parameter is measured with the use of the ClockLock or ClockBoost circuits.
parameters.
Table 36. EP1K10 External Bidirectional Timing Parameters
Symbol
Speed Grade
Unit
-1
-2
-3
Min
Max
Min
Max
Min
Max
2.2
2.3
3.2
ns
0.0
ns
2.0
6.6
2.0
7.8
2.0
9.6
ns
8.8
11.2
14.0
ns
8.8
11.2
14.0
ns
3.1
3.3
鈥�
0.0
鈥�
0.5
5.1
0.5
6.4
鈥�
ns
7.3
9.2
鈥�
ns
7.3
9.2
鈥�
ns
Table 37. EP1K30 Device LE Timing Microparameters (Part 1 of 2)
Symbol
Speed Grade
Unit
-1
-2
-3
Min
Max
Min
Max
Min
Max
tLUT
0.7
0.8
1.1
ns
tCLUT
0.5
0.6
0.8
ns
tRLUT
0.6
0.7
1.0
ns
tPACKED
0.3
0.4
0.5
ns
tEN
0.6
0.8
1.0
ns
tCICO
0.1
0.2
ns
tCGEN
0.4
0.5
0.7
ns
tCGENR
0.1
0.2
ns
tCASC
0.6
0.8
1.0
ns
tC
0.0
ns
tCO
0.3
0.4
0.5
ns
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