參數(shù)資料
型號： EM773FHN33,551
廠商： NXP Semiconductors
文件頁數(shù)： 31/51頁
文件大?。?/td> 0K
描述： IC ENERGY METER ARM 32VQFN
其它有關(guān)文件： EM773 Energy Metering IC Training
特色產(chǎn)品： EM773 Energy Metering IC
標準包裝： 260
核心處理器： ARM? Cortex?-M0
芯體尺寸： 32-位
速度： 48MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，WDT
輸入/輸出數(shù)： 25
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.6 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 32-VQFN 裸露焊盤
包裝： 托盤
配用： 568-6681-ND - BOARD EVAL EM773 METER EU PLUG
568-6680-ND - BOARD EVAL EM773 METER US PLUG
其它名稱： 568-5213
EM773
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 3 January 2012
37 of 51
NXP Semiconductors
EM773
Energy metering IC
[6]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA
output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the
SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.
[7]
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors
are used, designers should allow for this when considering bus timing.
[8]
The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than
the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if
the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the
data must be valid by the set-up time before it releases the clock.
[9]
tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in
transmission and the acknowledge.
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement
tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must
meet this set-up time.
10.7 SPI interface
Fig 19. I2C-bus pins clock timing
002aaf425
tf
70 %
30 %
SDA
tf
70 %
30 %
S
70 %
30 %
70 %
30 %
tHD;DAT
SCL
1 / fSCL
70 %
30 %
70 %
30 %
tVD;DAT
tHIGH
tLOW
tSU;DAT
Table 14.
Dynamic characteristics of SPI pins in SPI mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SPI master (in SPI mode)
Tcy(clk)
clock cycle time
full-duplex mode
50
-
ns
when only transmitting [1]
40
ns
tDS
data set-up time
in SPI mode
2.4 V
V
DD 3.6 V
15
-
ns
2.0 V
V
DD < 2.4 V
20
ns
1.8 V
V
DD < 2.0 V
24
-
ns
tDH
data hold time
in SPI mode
0-
-
ns
tv(Q)
data output valid time in SPI mode
--
10
ns
th(Q)
data output hold time in SPI mode
0-
-
ns
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