參數(shù)資料
型號(hào): EM6617DL28A
英文描述: Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: 0&degC to 70°C; Package: 8-SOIC T&R
中文描述: 微控制器
文件頁數(shù): 13/67頁
文件大?。?/td> 824K
代理商: EM6617DL28A
EM6617
03/02 REV. C/442
Copyright
2002, EM Microelectronic-Marin SA
20
www.emmicroelectronic.com
The EM6617 has one globally configurable Input / Output port which is 4 bit wide (only two bits are available for
24 pin packages). Input or output mode can be set by writing the bit PCIOCntl in RegPCCntl register.
“0“ = input mode (default), “1“ = output mode. The RegPCData register is used to write output data on port C.
Input data is read directly on the input terminal and put onto the internal data bus. It is not stored in the
RegPCData
register. The port C terminal status can be read on address RegPCData even in output mode. Be
aware that the data read on port C is not necessary of the same value as the data stored on RegPCData
register.
At any reset, the RegPCCntl register is cleared, thus setting the port in input mode. During SLEEP mode,
PC[3:0] are in high impedance state.
The port C is globally configurable to act as CMOS or Nch. open drain port , selectable in OPTPCandStr
register (NchOpDPC bit).
7.6.1 Pull-up or Pull-down
On each terminal of PC[3:0] an internal input pull-up (metal mask MPCPU[n]) or pull-down (metal mask
MPCPD[n]) resistor can be connected per metal mask option. Per default the two resistors are in place. In this
case one can chose per software to have either a pull-up, a pull-down or no resistor.
Figure 15. Port C Architecture
Open Drain Option
Register
Port C Direction Register
Port C Data Register
Internal Data Bus
Active
Pull-down
I / O Terminal
PC[n]
PCIOCntl
PCData[n]
DB[n]
Read
Read for PC[3:0]
Port C
Control
Active Pull-up
in Nch. Open
Drain Mode
Read
NoPdPC
Pull-down
Option Register
NchOpDPC
mask option
MPCPD[n]
Mask Option
MPCPD[n]
4
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EM6617SO28A Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: 0&degC to 70°C; Package: 8-EPSOIC T&R
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