
65 COM/ 132SEG Dot Matrix LCD Driver
6
EM65565A
(Continuous)
Pin Name
I/O
Function
# of
Pins
M/S = “H”: Master operation
M/S = “L”: Slave operation
The following is true depending on the M/S and DCLKS status:
M/S DCLKS
Oscillator
circuit
Power Supply
Circuit
DCLK
FR
FRS
/BCT
H
Enable
O
H
L
Disable
Enable
I
O
H
Disable
I
O
I
L
Disable
I
O
I
M/S
I
O: Output, I: Input
1
This is the display clock input terminal
The following is true depending on the M/S and DCLKS status.
M/S
DCLKS
DCLK
H
Output
H
L
Input
H
Input
L
Input
DCLK
I/O
When the EM65565A chips are used in master/slave mode, the various
DCLK terminals must be connected.
1
FR
I/O
This is the liquid crystal alternating current signal I/O terminal.
M/S = “H”: Output
M/S = “L”: Input
When the EM65565A Series chip is used in master/slave mode, the
various FR terminals must be connected.
2
/BCT
I/O
This is the LCD blanking control terminal.
M/S = “H”: Output
M/S = “L”: Input
When the EM65565A chip is used in master/slave mode, the various /BCT
terminals must be connected.
1
FRS
O
This is the output terminal for the static drive.
This terminal is only enabled when the static indicator display is ON when
in master operation mode, and is used in conjunction with the FR terminal.
1
IRS
I
This terminal selects the resistors for the V0 voltage level adjustment.
IRS = “H”: Use the internal resistors
IRS = “L”: Do not use the internal resistors. The V0 voltage level is
regulated by an external resistive voltage divider attached to the VR
terminal.
This pin is enabled only when the master operation mode is selected.
It is fixed to either “H” or “L” when the slave operation mode is selected.
1
/PCT
I
This is the power control terminal for the power supply circuit for liquid
crystal drive.
/PCT = “H”: Normal mode
/PCT = “L”: High power mode
This pin is enabled only when the master operation mode is selected.
It is fixed to either “H” or “L” when the slave operation mode is selected.
1