
65 COM/ 132SEG Dot Matrix LCD Driver
10
EM65565A
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3
1
2
3
4
5
6
7
8
9
10
11
12
13
/CS1
CS2
SI
SCL
D/I
Fig. 2
Notes:
1. When the chip is not active, the shift registers and counter are reset to their initial states.
2. Reading is not possible while in serial interface mode.
3. Caution is required on the SCL signal when it comes to line-end reflections and external
noise. We recommend that operation be rechecked on the actual equipment.
The Chip Select
The EM65565A chip have two chip select terminals: /CS1 and CS2. The MPU interface
or the serial interface is enabled only when /CS1=”L” and CS2=”H”.
When the chip select is inactive. D0 to D7 enter a high impedance state, and the D/I, /RD,
and /WR inputs are inactive. When the serial interface is selected. The shift register and the
counter are reset.
Accessing the DDRAM and the Internal Registers
In order to make matching of operation frequencies between the MPU and DDRAM or
internal register, the EM65565A performs a sort of LSI-LSI pipelining via the bus holder
attached to the internal data bus.
When the MPU writes data to the DDRAM, once the data is stored in the bus holder, then
it is written to the DDRAM before the next data write cycle. Moreover, when the MPU reads
the DDRAM, the first data read cycle (dummy) stores the read data in the bus holder, and
then the data is read from the bus holder to the system bus at the next data read cycle.
There is a certain restriction in the read sequence of the DDRAM. Please be advised that
data of the specified address is not generated by the read instruction issued immediately after
the address setup. This data is generated in data read of the second time. Thus, a dummy
read is required whenever the address setup or the write cycle operation is conducted. This
relationship is shown in Figure 3.