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| 型號(hào)： | EM6517 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 4位微控制器 |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER |
| 中文描述： | 4位單片機(jī)的小型通用紅外遙控器 |
| 文件頁數(shù)： | 34/66頁 |
| 文件大小： | 762K |
| 代理商： | EM6517 |
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EM6517
FOR ENGINEERING ONLY
EM Microelectronic-Marin SA, 09/99, Rev. A/277
34
The ADC is of bipolar type : Positive or negative input signal referred to the virtual ground point Vgnd are
converted. The virtual ground point Vgnd is ideally on (VSS + VBAT)/2 voltage level and must be supplied from
external circuitry.
The positive reference voltage VREF referred to the virtual ground point Vgnd defines the input voltage range
without overflow (full scale conversion : +/- Vref referred to Vgnd)
Data format is the following : MSB
ADCData[7]
is a sign bit indicating if input signal Vin is higher than virtual
ground (ADCData[7] = “1“) or lower (ADCData[7] = “0“).
For negative input signal the LSB’s are coded in 1’ complement.
For instance :
Vin = +VREF
Vin = +VREF/ 2
Vin = Vgnd
Vin = -VREF/ 2
Vin = -VREF
->
->
->
->
->
ADCData[7:0] = “1 1111111“
ADCData[7:0] = “1 0111111“
ADCData[7:0] = “1 0000000“
ADCData[7:0] = “0 1000000“
ADCData[7:0] = “0 0000000“
+127
+63
+0
-63
-127
The input channel to be converted is selected by
ChannelSelA
and
ChannelSelB
bits in
RegADCCntl
register.
The default channel selection is Vref as ADC input.
Setting to “1“ the
Vref1/2Sel
bit in
RegSysCntl 3
selects the internal V
DD
(Vref2 input) as the reference voltage.
By default, VREF is defined by the external Vref pad (Vref1 input).
The ADC has two working modes (continuous or single mode) selected by the
Single
bit (Single = “0“ -->
continuous mode ; Single = “1“ --> single mode).
10.1 Continuous mode
The conversion process is activated by setting to “1“ the
StartConvert
bit. The selected channel is cyclically
(3.2kHz) converted and the result is stored in
RegADCDataL
and
RegADCDataH
registers. When the
StartConvert
bit is set to “0“, the process runs until completion of the current 10 clock cycles and then stops.
After each completion, an interrupt request
IRQADC
is generated. This interrupt request can be masked
(default) (
MaskIRQADC
bit). See also the interrupt handling section 13 for further information. One always
needs to read
RegADCDataH
first , this read updates the
RegADCDataL
value (shadow register).
10.2 Single mode
Setting to “1“ the
StartConvert
bit activates 1 conversion of the selected channel. At the end of the conversion,
the
StartConvert
bit is automatically cleared and
IRQADC
is generated. Data are available in
RegADCDataL
and
RegADCDataH
registers. One always needs to read
RegADCDataH
first , this read updates the
RegADCDataL
value (shadow register).
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