參數(shù)資料
型號： EM6517
廠商： Electronic Theatre Controls, Inc.
元件分類： 4位微控制器
英文描述： 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER
中文描述： 4位單片機的小型通用紅外遙控器
文件頁數(shù)： 26/66頁
文件大小： 762K
代理商： EM6517
EM6517
FOR ENGINEERING ONLY
EM Microelectronic-Marin SA, 09/99, Rev. A/277
26
For instance, loading the counter in up count mode with hex 000 and the comparator with hex C52 which will
be identified as :
- bits[11:10] are limiting the counter to limits to 4 bits length, =03
- bits [9:4] are the unused counter bits = hex 05 (bin 000101),
- bits [3:0] (comparator value = 2).
(BitSel[1,0])
(number of PWM pulses)
(length of PWM pulse)
Thus after 5 PWM-pulses of 2 clocks cycles length the Counter generates an
IRQComp
and stops.
The same example with SelIntFull=0 (limited bit compare) will produce an unlimited number of PWM at a length
of 2 clock cycles.
8.5.1 How the PWM Generator works.
For Up Count Mode
; Setting the counter in up count and PWM mode the PB[3] PWM output is defined to be 0
(
EnComp
=0 forces the PWM output to 0 in upcount mode, 1 in downcount). Each Roll Over will set the output
to ‘1’ and each Compare Match will set it back to ‘0’. The Compare Match for PWM always only works on the
defined counter length. This, independent of the SelIntFull setting which is valid only for the IRQ generation.
Refer also to the compare setup in chapter 8.4.
In above example the PWM starts counting up on hex 0,
2 cycles later compare match -> PWM to ‘0’,
14 cycles later roll over -> PWM to ‘1’
2 cycles later compare match -> PWM to ‘0’ , etc. until the completion of the 5 pulses.
The normal IRQ generation remains on during PWM output. If no IRQ’s are wanted, the corresponding masks
need to be set.
In Down Count Mode
everything is inverted. The PWM output starts with the ‘1’ value. Each Roll Over will set
the output to ‘0’ and each Compare Match will set it back to ‘1’. For limited pulse generation one must load the
complementary pulse number value. I.e. for 5 pulses counting on 4 bits load bits[9 :4] with hex 3A (bin 111010).
8.5.2 PWM Characteristics
PWM resolution is
the minimal signal period is
the maximum signal period is : 1024 x Fmin*
the minimal pulse width is
* This values are for Fmax or Fmin derived from the internal system clock (32kHz). Much shorter (and longer)
PWM pulses can be achieved by using the port A as frequency input.
: 10bits (1024 steps), 8bits (256 steps), 6bits (64 steps) or 4 bits (16 steps)
: 16 (4-bit) x Fmax*
-> 16 x 1/Ck[15]
-> 1024 x 1/Ck[1]
: 1 bit
-> 1 x 1/Ck[15]
-> 977 μs
-> 1024 s
-> 61 μs
(32 KHz)
(32 KHz)
(32 KHz)
One must not use a compare value of hex 0 in up count mode nor a value of hex 3FF (or FF,3F, F if limited bit
compare) in downcount mode.
Figure 20. PWM Output in Up Count Mode
Data+2
Data+1
Data-1
Data
...
001
000
03F
03E
PWM output
IRQComp
IRQCount0
Compare
Roll-over
Count[9 :0]
Clock
Figure 21. PWM Output in Down Count Mode
Data-2
Data-1
Data+1
Data
...
3FE
3FF
000
001
PWM output
IRQComp
IRQCount0
Compare
Roll-over
Count[9 :0]
Clock
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