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參數(shù)資料
| 型號： | EM2420TR |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 2.4 GHz IEEE 802.15.4 / ZigBee RF Transceiver |
| 中文描述： | 2.4 GHz IEEE 802.15.4標準/ ZigBee的射頻收發(fā)器 |
| 文件頁數(shù)： | 84/89頁 |
| 文件大?。?/td> | 1758K |
| 代理商： | EM2420TR |
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EM2420
Ember Part Number: 120-0049-000
C
EM2420 Datasheet
Page 84 of 89
Test Output Signals
The two digital output pins SFD and CCA,
can be set up to output test signals
defined
by
IOCFG1.SFDMUX
and
IOCFG1.CCAMUX
. This is summarized in
Table 12 and Table 13 below.
SFDMUX
Signal output on
SFD
pin
Description
0
SFD
Normal operation
1
ADC_Q[0]
ADC, Q-branch, LSB used for random number generation
2
DEMOD_RESYNC_LATE
High one 16 MHz clock cycle each time the demodulator
resynchronises late
3
LOCK_STATUS
Lock status, same as
FSCTRL.LOCK_STATUS
4
MOD_CHIPCLK
Chip rate clock signal during transmission
5
MOD_SERIAL_CLK
Bit rate clock signal during transmission
6
FFCTRL_FS_PD
Frequency synthesizer power down, active high
7
FFCTRL_ADC_PD
ADC power down, active high
8
FFCTRL_VGA_PD
VGA power down, active high
9
FFCTRL_RXBPF_PD
Receiver bandpass filter power down, active high
10
FFCTRL_LNAMIX_PD
Receiver LNA / Mixer power down, active high
11
FFCTRL_PA_P_PD
Power amplifier power down, active high
12
AGC_UPDATE
High one 16 MHz clock cycle each time the AGC updates its gain
setting
13
VGA_PEAK_DET[1]
VGA Peak detector, gain stage 1
14
VGA_PEAK_DET[3]
VGA Peak detector, gain stage 3
15
AGC_LNAMIX_GAINMODE[1]
RF receiver front-end gain mode, bit 1
16
AGC_VGA_GAIN[1]
VGA gain setting, bit 1
17
VGA_RESET_N
VGA peak detector reset signa, active low.
18
-
Reserved
19
-
Reserved
20
-
Reserved
21
-
Reserved
22
-
Reserved
23
CLK_8M
8 MHz clock signal output
24
XOSC16M_STABLE
16 MHz crystal oscillator stabilised, same as the status bit in Table
5
25
FSDIG_FREF
Frequency synthesizer, 4 MHz reference signal
26
FSDIG_FPLL
Frequency synthesizer, 4 MHz divided signal
27
FSDIG_LOCK_WINDOW
Frequency synthesizer, lock window
28
WINDOW_SYNC
Frequency synthesizer, synchronized lock window
29
CLK_ADC
ADC clock signal 1
30
ZERO
Low
31
Table 12. SFD test signal select table
ONE
High
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相關代理商/技術參數(shù) |
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|---|---|
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