參數(shù)資料
型號(hào): EM2420TR
廠商: Electronic Theatre Controls, Inc.
英文描述: 2.4 GHz IEEE 802.15.4 / ZigBee RF Transceiver
中文描述: 2.4 GHz IEEE 802.15.4標(biāo)準(zhǔn)/ ZigBee的射頻收發(fā)器
文件頁(yè)數(shù): 25/89頁(yè)
文件大?。?/td> 1758K
代理商: EM2420TR
EM2420
Ember Part Number: 120-0049-000
C
EM2420 Datasheet
Page 25 of 89
4-wire Serial Configuration and Data Interface
The
EM2420
is configured via a simple 4-
wire SPI-compatible interface (pins
SI
,
SO
,
SCLK
and
CSn
) where the
EM2420
is
the slave. This interface is also used to
read and write buffered data (see page
37). All address and data transfer on the
SPI interface is done most significant bit
first.
Register access
There are 33 16-bit configuration and
status registers, 15 command strobe
registers, and two 8-bit registers to access
the separate transmit and receive FIFOs.
Each of the 50 registers is addressed by a
6-bit address. The RAM/Register bit (bit 7)
must be cleared for register access. The
Read/Write bit (bit 6) selects a read or a
write operation and makes up the 8-bit
address field together with the 6-bit
address.
In each register read or write cycle, 24 bits
are sent on the SI-line. The
CSn
pin (Chip
Select, active low) must be kept low during
this transfer. The bit to be sent first is the
RAM/Register bit (set to 0 for register
access), followed by the R/W bit (0 for
write, 1 for read). The following 6 bits are
the address-bits (A5:0
)
. A5 is the most
significant bit of the address and is sent
first. The 16 data-bits are then transferred
(D15:0), also MSB first. See Figure 8 for
an illustration.
The configuration registers can also be
read by the microcontroller via the same
configuration interface. The R/W bit must
be set high to initiate the data read-back.
The
EM2420
then returns the data from the
addressed register on the 16 clock cycles
following the register address. The
SO
pin
is used as the data output and must be
configured
as
an
microcontroller.
input
by
the
The timing for the programming is also
shown in Figure 8 with reference to Table
4. The clocking of the data on
SI
into the
EM2420
is done on the positive edge of
SCLK
. When the last bit, D0, of the 16
data-bits has been written, the data word
is loaded in the internal configuration
register.
Multiple registers may be written without
releasing
CSn
, as described in the Multiple
SPI access section on page 29.
The register data will be retained during a
programmed power-down mode, but not
when the power-supply is turned off (e.g.
by disabling the voltage regulator using
the
VREG_EN
pin). The registers can be
programmed in any order.
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