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參數(shù)資料
| 型號： | EM128L08T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 128Kx8 Bit Ultra-Low Power Asynchronous Static RAM |
| 中文描述： | 128Kx8位超低功耗異步靜態(tài)RAM |
| 文件頁數(shù)： | 5/7頁 |
| 文件大小： | 61K |
| 代理商： | EM128L08T |
Stock No. 23005-07 6/99
5
NanoAmp Solutions
EM128C08
TABLE 8: Timing - EM128C08-10 Version
FIGURE 3: Read Cycle Timing (WE = V
IH
)
Item
Symbol
1.5 to 3.6 V
1.8 to 3.6 V
2.7 to 3.6 V
3.0 to 3.6 V
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
t
AA
t
CE
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
500
300
120
100
ns
Address Access Time
500
300
120
100
ns
Chip Enable Access Time
500
300
120
100
ns
Output Enable to Valid Output
100
60
25
25
ns
Chip Enable to Low-Z output
0
0
0
0
ns
Output Enable to Low-Z Output
0
0
0
0
ns
Chip Disable to High-Z Output
0
100
0
60
0
25
0
25
ns
Output Disable to High-Z Output
0
100
0
60
0
25
0
25
ns
Output Hold from Address Change
10
10
10
10
ns
Write Cycle Time
500
300
120
100
ns
Chip Enable to End of Write
500
300
120
100
ns
Address Valid to End of Write
500
300
120
100
ns
Address Set-Up Time
0
0
0
0
ns
Write Pulse Width
300
100
50
40
ns
Write Recovery Time
0
0
0
0
ns
Write to High-Z Output
0
100
0
60
0
25
0
25
ns
Data to Write Time Overlap
300
80
40
30
ns
Data Hold from Write Time
0
0
0
0
ns
End Write to Low-Z Output
10
10
10
10
ns
A0-A16
CE1/CE2
OE
D0-D7
t
RC
t
CE
t
OE
t
OHZ
t
HZ
t
AA
Data Valid
t
LZ
t
OH
t
OLZ
Enable Valid
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