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參數(shù)資料
| 型號(hào)： | ELANSC310 |
| 英文描述： | Elan SC310 - Elan SC310 Single-Chip. 32-Bit. PC/AT Microcontroller |
| 中文描述： | 義隆SC310 -伊蘭SC310單芯片。 32位。的PC / AT單片機(jī) |
| 文件頁(yè)數(shù)： | 46/119頁(yè) |
| 文件大?。?/td> | 1167K |
| 代理商： | ELANSC310 |
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32
lanSC310 Microcontroller Data Sheet
PREL IMINARY
IRQ1, IRQ14
Interrupt Request Channels 1 and 14 (Input; Rising
Edge/Active High, with Internal Pullup)
This input is connected to the internal 8259A-compati-
ble Interrupt Controller Channels 1 and 14. In PC-com-
patible systems, IRQ1 may be connected to the 8042
keyboard controller.
MCS16
(Input; Active Low)
This input is used to signal to the ISA control logic that
the targeted memory device is a 16-bit device.
MCS16
is generated by a 16-bit memory expansion
card when the card recognizes it is being addressed.
This signal tells the data bus steering logic that the ad-
dressed memory device is capable of communicating
over both data paths. When accessing an 8-bit memory
device, the MCS16 line remains deasserted, indicating
to the data bus steering logic that the currently ad-
dressed device is an 8-bit memory device capable of
communicating only over the lower data path.
Note: MCS16 is internally OR’d with IOCS16. Do not tie
MCS16
Low.
For more information about the MCS16 pin, see the
Using 16-Bit ROMCS Designs in lanTMSC300 and
lanSC310 Microcontrollers Application Note, order
#21825.
MEMR
Memory Read Command (Output; Active Low)
The MEMR signal indicates that the current cycle is a
read of the currently selected memory device. When
this signal is asserted, the selected memory device can
drive data onto the data bus.
MEMW
Memory Write Command (Output; Active Low)
The MEMW signal indicates that the current cycle is a
write of the currently selected memory device. When
this signal is asserted, the selected memory device can
latch data from the data bus.
PIRQ0 (IRQ6)
PIRQ1 (IRQ3)
Programmable Interrupt Requests (Inputs; Rising
Edge/Active High, with Internal Pullup)
These two inputs can be programmed to drive any of
the available interrupt controller interrupt request in-
puts. For more information, see the corresponding
PIRQ Configuration Register, Index B2h, in the
lanTMSC310 Microcontroller Programmer’s Refer-
ence Manual, order #20665.
RSTDRV
System Reset (Output; Active High)
This signal is the ISA-compatible reset signal. When
this signal is asserted, all connected devices reinitialize
to their reset state. The pulse width of RSTDRV is ad-
justable based on PLL startup timings. For more infor-
mation, see “Loop Filters” on page 86 and the power-
up sequence timings beginning on page 88.
SA11–SA0
System Address Bus (Output; Active High)
The system address bus outputs the physical memory
or I/O port, least-significant, latched addresses. They
are used by all external I/O devices and all memory de-
vices other than main system DRAM. During main sys-
tem SRAM and local bus cycles, this bus represents
the CPU address bus (A11–A1). SA0 is equivalent to
A0 during local bus cycles. See MA11–MA0 on
page 30 for SA23–SA12.
SBHE
(Output; Active Low)
Active when the high byte is to be transferred on the
upper 8 bits of the data bus.
SPKR
Speaker, Digital Audio Output (Output)
This signal controls an external speaker driver. It is
generated from the internal 8254-compatible Timer
Channel 2 output ANDed with I/O port 061h, bit 1
(speaker data enable).
TC [TMS]
Terminal Count (Output; Active High)
This signal is used to indicate that the transfer count for
the currently active DMA channel has reached zero,
and that the current DMA cycle is the last transfer.
This is a dual-function pin. When the JTAGEN signal is
asserted, it will function as the TMS, JTAG Test Mode
Select pin. See the JTAG Interface section for more in-
formation on the function of this pin during Test mode.
KEYBOARD INTERFACE
8042CS [XTDAT]
Keyboard Controller Chip Select (Output; Active Low)
This signal is a decode of A9–A0 = 060h to 06Eh, all
even addresses. In PC-compatible systems, it con-
nects to the external keyboard controller chip select.
XTDAT is the PC/XT keyboard data line.
A20GATE
Address Bit-20 Gate (Input; Active High)
When deasserted (Low), A20GATE is used to force
CPU address bit 20 Low, a function required for PC
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相關(guān)代理商/技術(shù)參數(shù) |
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| ELANSC310-25 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip, 32-Bit, PC/AT Microcontroller |
| ELANSC310-25KC | 制造商:ADVANCED MICRO DEVICES,INC 功能描述: |
| ELANSC310-25KI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip, 32-Bit, PC/AT Microcontroller |
| ELANSC310-25VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: 制造商:AMD 功能描述: |
| ELANSC310-33 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip, 32-Bit, PC/AT Microcontroller |
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