- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄97905 > EL5285CS Dual and Window 4ns High-Speed Comparators PDF資料下載
參數(shù)資料
| 型號(hào)： | EL5285CS |
| 元件分類： | 比較器 |
| 英文描述： | Dual and Window 4ns High-Speed Comparators |
| 中文描述： | 雙窗口和4ns的高速比較器 |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大?。?/td> | 303K |
| 代理商： | EL5285CS |
7
EL5285C - Preliminary
Dual and Window 4ns High-Speed Comparators
E
L
52
85
C
-
P
re
lim
in
ar
y
Timing Diagram
VIN
VOD
th
ts
tpd-
tpw(D)
td+
Latch
Enable
Input
Latch
Compare
Latch
Compare
Differential
Input
Voltage
Comparator
Output
1.4V
VOS
2.4V
Definition of Terms
Term
Definition
VOS
Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output
VIN
Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications
VOD
Input Voltage Overdrive - Usually set to 50mV and in opposite polarity to VIN for comparator specifications
tpd+
Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
logic threshold of an output low to high transition
tpd-
Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
logic threshold of an output high to low transition
td+
Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
transition to the point of the output crossing CMOS threshold in a low to high transition
td-
Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
transition to the point of the output crossing CMOS threshold in a high to low transition
ts
Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be present in
order to be acquired and held at the outputs
th
Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain unchanged in
order to be acquired and held at the output
tpw (D)
Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an input signal
change
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EL5285CS-T7 | Dual and Window 4ns High-Speed Comparators |
| EL5285C | Replaced by PTN04050A : |
| EL5292CS-T13 | Dual 600MHz Current Feedback Amplifier |
| EL5292C | Replaced by PTN04050C : |
| EL5292CS | Replaced by PTN04050C : |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EL5285CS-T13 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual 4ns High-Speed Comparator |
| EL5285CS-T7 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual 4ns High-Speed Comparator |
| EL5285I | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual 4ns High-Speed Comparator |
| EL5287 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Window 4ns High-Speed Comparator |
| EL5287C | 制造商:ELANTEC 制造商全稱:ELANTEC 功能描述:Dual and Window 4ns High-Speed Comparators |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。