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2
EL5285C - Preliminary
Dual and Window 4ns High-Speed Comparators
E
L
52
85
C
-
P
re
lim
in
ar
y
Absolute Maximum Ratings (T
A = 25°C)
Absolute maximum ratings are those values beyond which the device
could be permanently damaged. Absolute maximum ratings are stress
ratings only and functional device operation is not implied.
Analog Supply Voltage (VS+ to VS-)
+12V
Digital Supply Voltage (VSD to GND)
+7V
Differential Input Voltage
[(VS-) -0.2V] to [(VS+) +0.2V]
Common-mode Input Voltage
[(VS-) -0.2V] to [(VS+) +0.2V]
Latch Input Voltage
-0.2V to [VSD+0.2V]
Storage Temperature Range
-65°C to +150°C
Ambient operating Temperature
-40°C to +85°C
Operating Junction Temperature
125°C
Power Dissipation
TBDmW
ESD Voltage
2kV
Important Note:
All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the
specified temperature and are pulsed tests, therefore: TJ = TC = TA.
Electrical Characteristics
VS = ±5V, VSD = 5V, RL = 2.3k, CL = 15pF, TA = 25°C, unless otherwise specified.
Parameter
Description
Condition
Min
Typ
Max
Unit
VOS
Input Offset Voltage
VCM = 0V, VO = 2.5V
2
4
mV
IB
Input Bias Current
8
15
A
CIN
Input Capacitance
5
pF
IOS
Input Offset Current
VCM = 0V, VO = 2.5V
100
500
nA
VCM
Input Voltage Range
(VS-) - 0.1
(VS+) - 2V
V
AVO
Large Signal Voltage Gain
5000
V/V
CMRR
Common-mode Rejection Ratio
-5V < VCM < +2.75V, VO = 2.5V
80
dB
PSRR
Power Supply Rejection Ratio
60
dB
VOH
Output High Voltage
VIN > 250mV
VSD - 0.5V
VSD - 0.4V
V
VOL
Output Low Voltage
VIN > 250mV
GND + 0.4V
GND + 0.5V
V
VLH
Latch Input Voltage High
2.0
V
VLL
Latch Input Voltage Low
0.8
V
ILH
Latch Input Current High
VLH = 3V
1
20
A
ILL
Latch Input Current Low
VLL = 0.3V
40
80
A
IS+
Positive Analog Supply Current
(per comparator)
10.5
mA
IS-
Negative Analog Supply Current
(per comparator)
7.5
mA
IDD
Digital Supply Current
(per comparator)
6
mA
td+
Positive Going Delay Time
VOD = 5mV, CL = 15pF, I O= 2mA
4
6
ns
td-
Negative Going Delay Time
VOD = 5mV, CL = 15pF, IO = 2mA
4
6
ns
tpd+
Latch Disable to High Delay
6
ns
tpd-
Latch Disable to Low Delay
8
ns
ts
Minimum Setup Time
2
ns
th
Minimum Hold Time
1
ns
tpw(D)
Minimum Latch Disable Pulse
Width
5
ns