參數(shù)資料
型號： EFM32TG110F32
廠商： Energy Micro
文件頁數(shù)： 51/136頁
文件大?。?/td> 0K
描述： MCU 32BIT 32KB FLASH 24-QFN
特色產(chǎn)品： EFM32 Tiny Gecko
標(biāo)準包裝： 1
系列： Tiny Gecko
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 32MHz
連通性： EBI/EMI，I²C，IrDA，智能卡，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 17
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x12b，D/A 1x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 24-VQFN 裸露焊盤
包裝： 標(biāo)準包裝
其它名稱： 914-1033-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
21
www.energymicro.com
the word instructions LDREX and STREX
the halfword instructions LDREXH and STREXH
the byte instructions LDREXB and STREXB.
Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.
To perform a guaranteed read-modify-write of a memory location, software must:
1. Use a Load-Exclusive instruction to read the value of the location.
2. Update the value, as required.
3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location, and
tests the returned status bit. If this bit is:
0
The read-modify-write completed successfully,
1
No write was performed. This indicates that the value returned at step 1 (p. 21) might be out
of date. The software must retry the read-modify-write sequence,
Software can use the synchronization primitives to implement a semaphores as follows:
1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the
semaphore is free.
2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore address.
3. If the returned status bit from step 2 (p. 21) indicates that the Store-Exclusive succeeded then the
software has claimed the semaphore. However, if the Store-Exclusive failed, another process might
have claimed the semaphore after the software performed step 1 (p. 21) .
The Cortex-M3 includes an exclusive access monitor, that tags the fact that the processor has executed
a Load-Exclusive instruction.
The processor removes its exclusive access tag if:
It executes a CLREX instruction
It executes a Store-Exclusive instruction, regardless of whether the write succeeds.
An exception occurs. This means the processor can resolve semaphore conflicts between different
threads.
For more information about the synchronization primitive instructions, see Section 3.4.8 (p. 54) and
2.2.8 Programming hints for the synchronization primitives
ANSI C cannot directly generate the exclusive access instructions. Some C compilers provide intrinsic
functions for generation of these instructions:
Table 2.14. C compiler intrinsic functions for exclusive access instructions
Instruction
Intrinsic function
LDREX
, LDREXH, or
LDREXB
unsigned int __ldrex(volatile void *ptr)
STREX
, STREXH, or
STREXB
int __strex(unsigned int val, volatile
void *ptr)
CLREX
void __clrex(void)
The actual exclusive access instruction generated depends on the data type of the pointer passed to
the intrinsic function. For example, the following C code generates the require LDREXB operation:
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