參數(shù)資料
型號: EFM32G222F128
廠商: Energy Micro
文件頁數(shù): 95/136頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 128KB FLASH 48LQFP
特色產(chǎn)品: EFM32 Gecko
標(biāo)準(zhǔn)包裝: 1
系列: Gecko
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 32MHz
連通性: I²C,IrDA,智能卡,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 37
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b,D/A 1x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 914-1027-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
61
www.energymicro.com
RRX
moves the bits in register Rm to the right by 1.
In all these instructions, the result is written to Rd, but the value in register Rm remains unchanged. For
details on what result is generated by the different instructions, see Section 3.3.4 (p. 39) .
3.5.3.3 Restrictions
Do not use SP and do not use PC.
3.5.3.4 Condition flags
If S is specified:
these instructions update the N and Z flags according to the result
the C flag is updated to the last bit shifted out, except when the shift length is 0, see Section 3.3.4 (p.
3.5.3.5 Examples
ASR
R7, R8, #9
; Arithmetic shift right by 9 bits
LSLS
R1, R2, #3
; Logical shift left by 3 bits with flag update
LSR
R4, R5, #6
; Logical shift right by 6 bits
ROR
R4, R5, R6
; Rotate right by the value in the bottom byte of R6
RRX
R4, R5
; Rotate right with extend
3.5.4 CLZ
Count Leading Zeros.
3.5.4.1 Syntax
CLZ{cond} Rd, Rm
where:
cond
is an optional condition code, see Section 3.3.7 (p. 43) .
Rd
is the destination register.
Rm
is the operand register.
3.5.4.2 Operation
The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd.
The result value is 32 if no bits are set in the source register, and zero if bit[31] is set.
3.5.4.3 Restrictions
Do not use SP and do not use PC.
3.5.4.4 Condition flags
This instruction does not change the flags.
3.5.4.5 Examples
CLZ
R4,R9
CLZNE
R2,R3
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